[SI-LIST] Re: What is probability distribution for logic switching

Hi Mike,

Thanks for the reply.

Yes, that is the question, and yes, it is vendor to vendor (TSMC in our
case).

I was reading an article this weekend about Single-wafer processing
equipment,
in IEEE Spectrum, Feb 2005, and found something again related to the OCV,
and
in particular, Vt...

On page-43 they mention (no hard numbers) how the annealing process can have
a variance of temperature across wafers and even a variance across a die
such
that the threshold voltage is different. If I am not mistaken, Kai's
original
post was in regards to the switching levels (Vt)!

Regards,
Jim

-
Jim Antonellis   janton@xxxxxxxxxxxxx
Sandburst Corp   www.sandburst.com
Office: 978.689.1669
Cell: 978.618.4745

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-----Original Message-----
From: Mike Brown [mailto:bmgman@xxxxxxxxxx]
Sent: Friday, March 18, 2005 10:18 PM
To: Jim Antonellis; kalevi@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: What is probability distribution for logic
switching


Jim,

I wholeheartedly agree.  There certainly IS a process variation from
gate to gate on a single die, but the spread is nowhere near
best-to-worst process.  I wasn't advocating complete disregard for
process variation, merely allowing for a smaller range of it.  The issue
is "How big is that OCV ?".  Only your chip vendor knows for sure, and
that's not even for sure.  For sure, the problem is exacerbated at
smaller process geometry.

It's a good thing that the timing tools now handle it.  There was a time
when that wasn't so, and I've had to kluge libraries with supposedly
appropriate OCV delays.

Regards

Mike

Jim Antonellis wrote:

>Hi Mike,
>
>In regards to your comment: "On a single die, not only the power and
>temperature are common-mode, but so is the process used to fabricate
>the die."... my 2-cents:
>
>I certainly concur that we will not see the two extremes... but, in
>.13um and below we are seeing what some term as "On Chip Variation"
>that accounts for slight PVT variations on a die. The voltage and
>temp variations (gradients) are fairly easy to buy, but in fact the
>process can change on a single die (e.g. due to differing stepper
>directions on the different sides of a die). Third party ASIC tools
>for timing and PD incorporate OCV today.
>
>Regards,
>Jim
>
>-
>Jim Antonellis   janton@xxxxxxxxxxxxx
>Sandburst Corp   www.sandburst.com
>Office: 978.689.1669
>Cell: 978.618.4745
>
>This message and any attachments are Confidential and may be Legally
>Privileged. It is intended solely for the addressee. If you are not
>the intended recipient, please delete this message from your system
>and notify us immediately. Any dis-closure, copying, distribution or
>action taken or omitted to be taken by an unintended recipient in
>reliance on this message is prohibited and may be unlawful.
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mike Brown
>Sent: Thursday, March 17, 2005 7:57 PM
>To: kalevi@xxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: What is probability distribution for logic
>switching
>
>
>Kai,
>
>I'm not sure that statistics is a good approach here.  It used to be
>that a clock-to-clock path often involved multiple chip crossings, and
>you could appeal to an RMS delay calculation to pull you out of a
>negative slack situation. This appeal is justified by the (presumably)
>independent process points of the chips in the path.  Most modern
>designs take a signal from a source chip and wire it directly to a
>destination chip.  There's no intervening logic to justify appealing to
>a statistical spread.
>
>If you are talking about timing a system, there's little to do except
>adjust the vendor's best and worst case numbers for any common-mode
>effects: power and/or temperature.  This because in general two
>different parts on a board can come from different lots (or even
>different vendors) at different process extremes.  It isn't always easy
>to find a Kv or Kt factor to use in this derating.  This approach can
>give you some comfort in living with the calculated negative slack.
>
>On a single die, not only the power and temperature are common-mode, but
>so is the process used to fabricate the die.  It is a fact that you
>can't get worst case slow and best case fast on the same die in a fixed
>environment.  The short/fast paths on a worst-case slow PVT die won't be
>anywhere best-case fast - but they will not be worst-case slow either.
>
>There's only one vendor that I know of that acknowledges that fact, and
>provides timing models that reflect it.  That vendor is IBM.  Most chip
>vendors steadfastly proclaim that the short (early) paths are worst-case
>slow, also.  I've used a "tracking factor" of 10% to derate the short
>paths on a slow PVT, or the long paths on a fast PVT analysis.  This is
>somewhat of a SWAG, based on some old data I once ran across.
>
>I believe that 0 derating is flat wrong;  I've seen data on a GaAs
>process stating 17% spread in on-die delay variation (IIRC).  I can
>justify a perhaps 2% voltage spread and perhaps a 10C variation in Tj
>across a die - and that calculates out to a (technology-dependent)
>number between 8-15% delay change.  I'd guess that 20% or more
>adjustment  is overly conservative.  Pick your poison, or find a vendor
>who can support the cross-die timing skew that is present.
>
>Regards
>
>Mike
>
>Kai Keskinen wrote:
>
>
>
>>A little question about probability here:
>>
>>When we do static timing analysis (STA) using simulation tools, we extract
>>the flight times with buffer delay compensation for a rising edge  with
the
>>minimum time being when the signal goes through VinL and the maximum time
>>being when the signal goes through VinH. Does anyone know what kind of
>>probability distribution there is for when the device actually switches?
>>Let's assume we are taking about CMOS and use a rising edge as an example.
>>Assume no noise or cross-talk, just a nice quiet receiver getting a nice
>>clean edge.
>>
>>Does anyone have a good reference for doing statistical timing analysis?
>>What I mean is calculating the likelyhood of a timing failure occurring if
>>the STA has shown a negative margin. With the faster clock speeds, we are
>>getting more negative margins with one or more corner cases and sometimes,
>>there appears to be no reasonable fix to get positive timing for all
cases.
>>
>>Any suggestions will be greatly appreciated.
>>
>>Kai
>>
>>
>>
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