Dear experts, I am designing a system where two Xilinx FPGAs on 2 separate PCBs will be connected with a differential serial 2.24 Gb/s RocketIO link. The cards are so called front and rear Compact PCI cards and are expected to go into a standard PICMG 2.16 chassis. Thus, they will be connected with a 2mm Hard Metric "pass-through" connector. In other words there will be a backplane or rather a midplane between the cards, but no tracks on this midplane, the signals will pass directly through the vertical male connector pins sticking out on both sides of the plane, while each of the cards will have a right angle female connector. My questions are as follows: 1. Has anyone done this successfully? 2. Which connector pins should I use for signaling and which for GND? 3. Can I get away without simulating this? If not, could someone please point me to where I can get appropriate SPICE(?) models for the connectors? Thanks, ======================= Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: (613) 271-0044 ext.231 Fax: (613)271-3007 http://www.squarepeg.ca ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu