[SI-LIST] Re: Routing guidelines for 3.12Gbps LVDS pairs

  • From: "Lambert Simonovich" <bertsimonovich@xxxxxxxxxx>
  • To: "'chundi srikanth'" <chundis@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 16 Oct 2009 16:56:35 -0400

Srikanth,

A rough rule of thumb is greater than 3 times trace width separation between
pairs. Using a 2D field solver will ultimately give you the crosstalk
coupling factor for the exact geometry in your stackup, and dictate the
routing rules you need to follow to satisfy your noise budget. 

Adding GND guarding will more often than not present more issues than it
solves. You should stitch these guard traces at regular intervals
approximately 1/10 of the wavelength of the highest frequency component of
the aggressor signal to avoid it from resonating and coupling noise back
onto other adjacent traces. This further reduces routing density of the
board. By the time you factor in the additional space of one trace width
between the guard trace and Diff pair, plus the additional via stitching,
you will find you are already at 3 times separation between pairs and you
would gain back more real estate.

Regards,

Bert Simonovich



   

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of chundi srikanth
Sent: October-16-09 12:40 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Routing guidelines for 3.12Gbps LVDS pairs

Hi Techies,
We have a 12-layer board in which we have lot of differential LVDS pairs
operating at several hundreds MHz. And we have SERDES signals (differential
TX & RX pairs) operating at CPRI rate-4 i.e., 3Gbps. So can you just share
me some inputs on exactly what are the guidelines to be followed  while
routing these signals. And is GND gaurding between the differential pairs
improve the SI?Please share or refer me any documents in which i can get
Good information on High-Speed design guidelines.

Thanks

With Best Regards
Srikanth


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