[SI-LIST] Re: Question on SI measurement/validation without receiver access
- From: "Douglas Burns" <dburns@xxxxxxxxxx>
- To: <arsenault_brian@xxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 29 Sep 2004 13:42:10 -0400
Brian,
For the configuration proposed (Back to back mounting) of a DDR device, we
can assume that some of the signals are shared between the 2 devices
(Address/Control) and some may or may not be shared (Data).
For the shared signals:
One of the devices could be removed from the board and measurements
taken.
This could then be correlated with simulations. This now gives you
confidence in the models and your ability to believe the simulations of the
dual mounted device.
For unshared signals:
1) Is there the ability to use through-hole via's for some of the
signals
to be tested. If so, then the depopulating method may be used.
2) If the signal is totally hidden, can some of the IO along the
periphery
of the chip be connected to a test pad. This may affect some performance
charcteristics, but allows you to validate simulations. The test pad could
be removed for production boards.
3) If neither of these options are available
a) Make measurements to the nearest via available. This may
require that
you insert extra via's in a net in order to get access to a test point. The
issue with this is that there could be plateaus (depending upon the
termination scheme) and depending upon the distance of the via to the load,
the plateau width could be on the order of the data rate. This would make
making measurements difficult at best.
b) Build a load card that has the same footprint and loading as
the device
under test, but that has visibility points.
c) Build a test ASIC that allows you to vary the switching
reference
voltage and the data capture point. With this you can construct an estimate
of the EYE opening and this can be compared with a simulated environment.
Each of these solutions trades off measurement precision verse cost and
complexity. Such is the price of knowledge
Doug
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of arsenault, brian
Sent: Wednesday, September 29, 2004 11:02 AM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Question on SI measurement/validation without
receiver access
Folks...
I'm looking for some suggestions and ideas on how to perform SI measurements
and correlate them to simulations when you don't have access to the receiver
pin.
For example, one of our designs is looking at back-to-back mounting of DDR-2
memory chips, and based on the spacing of the board, the vias close to the
receivers (the RAM's, when a read operation takes place) will not be
accessible. The same thing would apply to probing signals at a receiver
that is using blind and buried vias.
Traditionally, all of our technology has utilized only through-vias, and we
have been able to probe directly on the pins of the receivers if a via was
not located very close by. As we're moving forward, it's apparent that we
need to find a better way to both show the designer that his/her design will
work, and for the SI group to correlate their simulations to measurements.
I'm aware that building a test card to validate the buffers is one way to
go, but in these times, we are trying to minimize extra costs.
Thanks...
Brian
Brian Arsenault
Principal HW Engineer
EMC Corporation
Hopkinton, MA
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