[SI-LIST] Re: Question on SI measurement/validation without receiver access

  • From: HaroldLSJ@xxxxxxx
  • To: arsenault_brian@xxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Wed, 29 Sep 2004 13:01:09 EDT

 
Brian,
 
First, measure the active (powered) input impedance of your receiver  over a 
frequency sweep at least ten times higher than your range of  interest.  Next, 
synthesize a network equal to this impedance sweep.   Now build a small 
daughter board the same size as your receiver component with  at least 5 
adjacent 
traces terminated with the synthesized network.   Depending on the size of the 
network you may have to realize it in thin film  and/or chip and wire 
technology.  This daughter board technique will allow  you to directly measure 
the SI 
characteristics of the incoming signal and  compare it to your simulations.  
The daughter board can be fitted with BGA  style balls on the bottom side at a 
number of places such as IC Interconnect in  Colorado.
 
Harold L. Snyder, Jr.
Scientist & Consultant
 
Begin Included Message dated 9/29/2004 10:06:17 AM Central Daylight Time,  
arsenault_brian@xxxxxxx writes:
===============================
Folks...

I'm looking for some suggestions and ideas on how to  perform SI measurements
and correlate them to simulations when you don't  have access to the receiver
pin.

For example, one of our designs is  looking at back-to-back mounting of DDR-2
memory chips, and based on the  spacing of the board, the vias close to the
receivers (the RAM's, when a  read operation takes place) will not be
accessible.  The same thing  would apply to probing signals at a receiver
that is using blind and buried  vias.

Traditionally, all of our technology has utilized only  through-vias, and we
have been able to probe directly on the pins of the  receivers if a via was
not located very close by.  As we're moving  forward, it's apparent that we
need to find a better way to both show the  designer that his/her design will
work, and for the SI group to correlate  their simulations to measurements.

I'm aware that building a test card  to validate the buffers is one way to
go, but in these times, we are trying  to minimize extra costs.

Thanks...

Brian


Brian  Arsenault
Principal HW Engineer
EMC Corporation
Hopkinton,  MA






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End Included Message.
 
 
 
 
 
 
 


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