[SI-LIST] Processor Data bus topology

From: "Balakrishnan K" <kbkrishnan@xxxxxxxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Wed, 25 Dec 2002 16:30:41 +0530

Hi all,
I have a processor data bus shared between FLASH,2 SDRAM,and a
transceiver,
the processor bus is at 66MHz
I have the following dobuts
1.Should i have series termination resistor on both end(porceesor end
and memory devices end)
2.  What topology should i follow for better layout

Thanks and regards
Bala




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[SI-LIST] Processor Data bus topology

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