[SI-LIST] Re: Processor Data bus topology
- From: "Binosh Balachandra" <binoshbc@xxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>, <kbkrishnan@xxxxxxxxxxxxxxx>
- Date: Wed, 25 Dec 2002 17:26:43 +0530
** Proprietary **
Hi Bala,
I feel that you should go for a series termination resistor ( probably =
you can use resistor arrays) near the processor end. Also your bus speed =
is only 66MHz.
You can go for a 8 layer or 10 layer board depending on your component =
density. You should have minimum 2 ground layers. Place the components =
such a way that bus routing can be done with out putting more vias. That =
helps a lot in reducing SI issues. As far as possible place the components =
so that track length is minimum.
Regards,
BBC
>>> "Balakrishnan K" <kbkrishnan@xxxxxxxxxxxxxxx> 25/12/2002 4:30:41 pm =
>>>
Hi all,
I have a processor data bus shared between FLASH,2 SDRAM,and a
transceiver,
the processor bus is at 66MHz
I have the following dobuts
1.Should i have series termination resistor on both end(porceesor end
and memory devices end)
2. What topology should i follow for better layout
Thanks and regards
Bala
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