[SI-LIST] Re: Processor Data bus topology
- From: "scuba snail" <scubasnail@xxxxxxxxxxx>
- To: kbkrishnan@xxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 25 Dec 2002 19:52:36 -0800
Dear Bala,
With your permission, I will assume the following:
1. Since the bus is shared, I reckon that each device will be used at a
time,and that will be achieved by arbitrating the devices with chip select
signals.
2. In addition, you should mind the fact that each device has a different
input capacitance.
The SDRAM input capacitance can be in the neighborhood of 5pf, the flash
around 7.5pf and the transceiver can get even to 10 or more pf.
3. It might be that each device is working in a different bus speed, again,
the SDRAM can use the whole 66MHz, and the transceiver can be much lower.
Having said that I would recommend to Daisy Chain them, in the following
fashion:
|\________________________________________
|/ | |
|
Processor Transceiver FLASH SDRAM
Even though they are Daisy Chained, they will not operate at the same time,
Iwould put the SDRAM at the end to avoid stubs.
As for termination ? you can use a series termination at the processor side,
and maybe at the SDRAM side. I would recommend some simulation to verify the
necessity of them.
Placement and Routing ? You should aim to have no to minimum traces from the
main ?trunk? to the ?branches? (loads).
Regards,
Gil G
Gil Gafni gil.gafni@xxxxxxxx (408) 605 8166 From: "Balakrishnan K" Reply-To:
kbkrishnan@xxxxxxxxxxxxxxx To: "si-list@xxxxxxxxxxxxx" Subject: [SI-LIST]
Processor Data bus topology Date: Wed, 25 Dec 2002 16:30:41 +0530 Hi all, I
have a processor data bus shared between FLASH,2 SDRAM,and a transceiver,
theprocessor bus is at 66MHz I have the following dobuts 1.Should i have
series termination resistor on both end(porceesor end and memory devices
end)2. What topology should i follow for better layout Thanks and regards
Bala ------------------------------------------------------------------ To
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