Hi all, I have a processor data bus shared between FLASH,2 SDRAM,and a transceiver, the processor bus is at 66MHz I have the following dobuts 1.Should i have series termination resistor on both end(porceesor end and memory devices end) 2. What topology should i follow for better layout Thanks and regards Bala ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu