[SI-LIST] Re: Power plane coupling

Steve,

I appreciate the feedback.  Having read your DesignCon paper that
addressed spreading inductance on big FPGAs and applied it on a previous
design, I should have mentioned in my email that the assumption was that
the distance from the center of the component to the capacitor in the
X-Y direction is the same and therefore the spreading inductance was
assumed to be equivalent.  The variable was whether the cap should be
placed on the top or bottom of the board when the VCC plane had to be on
the opposite side of the stack from the device.

Incidentally, I can't find that paper since I changed employers (the CD
is in a box somewhere).  Can you email me a copy?  I would like to do
the math to quantify things a bit.

Thanks,
Chris


>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]
>Sent: Friday, October 21, 2005 4:11 PM
>To: Mcgrath, Christopher; LSMITH@xxxxxxxxxx;
ludovic.levieil@xxxxxxxxxxx;
>si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Power plane coupling
>
>Chris,
>
>You always want to think in terms of minimizing demon inductance. So,
first
>we want to put the plane(s) that support our lowest impedance
requirements
>closest to the device they feed.  Not every plane can be in the top of
the
>stack, so this will compromise some supplies.
>
>The placement of capacitors should also be selected to minimize the
total
>inductance between the caps and the devices they serve.  For a plane
>towards the bottom of the board, this means the caps go on the bottom.
We
>are already burned by the long vias from the device to a plane near the
>opposite side of the board.  If we place the caps on the same side as
the
>part, then the attachment vias for the caps will be just as long, a
very
>bad thing.
>
>Spreading inductance is another issue.  It is part of the price we pay
for
>the reality that it is essentially impossible to put discrete caps of
any
>size right on the die pads.  The further we move away in any axis, the
>higher a penalty we pay.  The natural log behavior of spreading
inductance
>and resistance is such that once we are in for a dime, we might as well
be
>in for a dollar.
>
>Regards,
>
>
>Steve.
>At 01:32 PM 10/21/2005 -0700, Mcgrath, Christopher wrote:
>>Larry,
>>
>>I have a related question that popped into my head when I read your
>>response.
>>
>>If you expand this example so that there were a number of layers
between
>>VCC1 and VCC2 which included both ground and signal layers so that the
>>thickness of the board begins to become significant with respect to
the
>>placement of decoupling capacitors, is the preferred location for
>>decoupling of a device placed on the top side of the PCB on the top
side
>>or bottom side of the board IF the voltage being decoupled is VCC2.
>>
>>At issue is whether it is better to place the decoupling capacitor
>>closer to the voltage it is decoupling or closer to the device that is
>>actually receiving the power.
>>
>>I believe that the path with the least inductance and maximum
>>effectiveness would be to place the decoupling capacitor on the top
side
>>of the board right next to the device.  While the spreading inductance
>>should be very similar in both cases, the loop inductance would be
>>slightly less when the cap is placed on the top of the board. =3D20
>>
>>Any thoughts?
>>
>>Thanks,
>>Chris
>>
>>=3D20
>>
>> >-----Original Message-----
>> >From: si-list-bounce@xxxxxxxxxxxxx
>>[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>> >Behalf Of Larry Smith
>> >Sent: Friday, October 21, 2005 12:05 PM
>> >To: ludovic.levieil@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> >Subject: [SI-LIST] Re: Power plane coupling
>> >
>> >Ludovic - I like this power plane stackup sequence, particularly if
it
>> >is on the top or bottom surface of the PCB.
>> >
>> >The power planes will be highly coupled to ground by discrete
>>decoupling
>> >capacitors mounted on the surface of the board.  There are probably
>> >100's of uF that are trying to maintain a constant voltage between
VCC1
>> >and Gnd, also between VCC2 and Gnd.  But the internal plane to plane
>> >capacitance is on the order of 1nF, not much compared to the
external
>> >capacitance.  At 100MHz, the 1 nF plane-to-plane impedance is about
>> >1/(2*pi*100e+6*1e-9) =3D3D3D 1.59 Ohms.  This is not strong compared
to =3D
>>the
>> >impedance of the PDS which is probably in the mOhms.  The impedance
>> >division insures that there will not be substantial noise coupled
from
>> >one power plane to the other in this stackup.  But as Istvan has
>> >commented in another note on this thread, this might not be best for
a
>> >sensitive analog supply or PLL circuitry.  Further filtering should
be
>> >used for those supplies.
>> >
>> >Noise above 100 MHz usually gets onto a power plane because of
>> >transmission line return current.  I like your stackup because the
>>power
>> >planes are surrounded by Gnd planes.  You have an opportunity for
>> >transmission lines to reference only ground planes throughout the
rest
>> >of the stackup.  This keeps the return current noise off the power
>> >planes and the power plane noise off the transmission lines.  Skin
>> >effect in solid ground planes greatly attenuates magnetic fields
from
>> >penetrating through the planes at 1 MHz and above.
>> >
>> >Noise below 100 MHz is usually caused by current transients from the
>> >loads.  A well designed PDS will be below target impedance from some
>> >corner frequency (50 to 100 MHz) all the way down to DC.  The noise
>> >coupled between power planes below this corner frequency is
diminished
>> >because the impedance of the plane-to-plane capacitance diminishes
at
>> >lower frequency.  This stackup puts you well on the way towards good
>> >power and signal integrity in your product.
>> >
>> >Regards,
>> >Larry Smith
>> >Altera Corporation
>> >(Sun Microsystems was very good for me, but it was time to move on.)
>> >
>> >-----Original Message-----
>> >From: si-list-bounce@xxxxxxxxxxxxx
>>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>> >On Behalf Of Ludovic Levieil
>> >Sent: Thursday, October 20, 2005 1:12 AM
>> >To: si-list@xxxxxxxxxxxxx
>> >Subject: [SI-LIST] Power plane coupling
>> >
>> >Hello All,
>> >In my current board design I have the following stack up:
>> >
>> >    .......
>> >---------------- GND (solid plane)
>> >------ ----- --- VCC1 (splitted plane)
>> >--- ----- ------ VCC2 (splitted plane)
>> >---------------- GND (solid plane)
>> >   .......
>> >
>> >4 mils separate GND and VCC planes
>> >5 mils separate VCC1 and VCC2 planes
>> >
>> >Both VCC planes are splitted in different power domains and I am
>> >wondering=3D3D20
>> >:
>> >        - if having two coupled VCC planes is good/acceptable
when=3D3D20
>> >thinking about noise ??
>> >        - if there is a problem in having one power domain on on
>>plane=3D3D20
>> >overlapping at least  two power domains on the other plane ??
>> >
>> >Thanks
>> >
>> >Ludovic Levieil=3D3D20
>> >
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