[SI-LIST] Re: Power plane coupling
- From: "Larry Smith" <LSMITH@xxxxxxxxxx>
- To: "steve weir" <weirsi@xxxxxxxxxx>, <christopher.mcgrath@xxxxxxxxx>, <ludovic.levieil@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 25 Oct 2005 17:47:58 -0700
Steve - I used to have the luxury of being able to control all 3
inductances. I agree with you that most PCB designers can only control
2 of the 3 because they cannot control the package design. This is
where the chip/package design houses have to understand things from the
system perspective and make sure they leave adequate inductance budget
for the PCB designers. =20
I'll do what I can to make that happen at this chip/package company. :)
Regards,
Larry Smith
Altera Corporation
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]=20
Sent: Tuesday, October 25, 2005 3:24 PM
To: Larry Smith; christopher.mcgrath@xxxxxxxxx;
ludovic.levieil@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Power plane coupling
Larry, as usual you offer very good advice. I would just comment a
little=20
bit about the difference between optimization, and realization.
Given the chance to independently control all three: a. IC package
design,=20
b. Board stack-up, and c. Bypass capacitor selection, and count I agree=20
that portioning in about equal amounts likely optimizes the=20
economics. However, a board designer is pretty much stuck with only b)
and=20
c) as the available variables. So to me the issue is one of
realization:
1. Can I come up with a PDS that actually works as needed?
2. What is the least cost way to get there?
To answer 1) I find that it is useful to take the target inductance you=20
have broken into three pieces, and evaluate the attachment from the IC
to=20
any given proposed location of the supporting planes in the stack-up.
If=20
this is more than half of the target, we are facing thin planes and/or a
lot of capacitors. If it is over two thirds, it may be difficult if not
impossible to realize a working design at any cost. After that, it is
an=20
iterative process of solving for each plane pair, and the resulting
bypass=20
network. If the package attachment strips the budget to where lots of
caps=20
and thin dielectric are needed, then I will use those to get through the
day as needed.
Best Regards,
Steve.
At 01:59 PM 10/25/2005 -0700, Larry Smith wrote:
>Chris - As you and Steve have mentioned, the best side of the board for
>placement of decoupling capacitors is a function of inductance. There
>are three important inductances involved, each of which play a
different
>roll.
>
>1) The capacitors are attached to the PCB with a mounting inductance
>that is closely related to the via length from the cap pads to the
>power/ground plane pair. The mounting inductance is an important
factor
>in determining the resonant frequency and Q of the mounted capacitor.
>For this reason, you want the power/ground plane pair to be as close as
>possible to the front or back surface of the PCB. In the stackup under
>discussion in this thread, that would be layers 2, 3, 4 and 5 (or N-1
>through N-4 where N is the number of layers). I like to use a matrix
of
>different valued capacitors, each with a similar mounting inductance,
to
>establish a low and flat impedance from about 1MHz to 100MHz for a bank
>of capacitors attached in this way.
>
>2) The power/ground plane pair is the conduit that carries power from
>the bank of capacitors (above) to the vicinity of the load. Istvan
>mentioned the value of thin power plane dielectric (Vcc to Gnd) to
>maximize plane capacitance. Thin dielectric also has superior
>inductance properties because the power plane spreading inductance is
>proportional to the dielectric thickness. The second important
>inductance in our problem is the horizontal power plane spreading
>inductance.
>
>3) Charge that is stored in the capacitors flows vertically through the
>mounting inductance, horizontally through the plane spreading
inductance
>and once again goes vertical in the vicinity of the load. A
>checkerboard pattern of power and ground vias is often used underneath
a
>load (i.e. BGA package) to form a low inductance path from the power
>planes to the power consumer. This is the third inductance in our
>problem.
>
>These three inductances should be closely balanced in the power
>distribution system because any one of them can dominate. I have seen
>cases where hundreds of power/ground vias underneath the BGA load have
>far less parallel inductance than the horizontal power plane spreading
>inductance, even when the vias carried current all the way from the
>backside of the board. Thin power plane dielectric could be very
>valuable for this system. But if there are not very many power and
>ground vias in the BGA pattern, there is no point in using thin power
>plane dielectric.
>
>The sum of inductances 2 and 3 gives a series inductance for the bank
of
>decoupling capacitors mounted on the board and gives an upper limit to
>the number of decoupling capacitors that are useful. The equivalent
>inductance of all the parallel decoupling capacitors should be
>calculated (mounting inductance divided by the number of caps). In a
>well designed power distribution system, about 1/3 of the inductance
>should be allocated to the BGA vias, 1/3 for the power planes and 1/3
>for the parallel mounting inductances. If one of these three
>inductances significantly dominates, it establishes the performance of
>the PDS and there is no point in putting additional cost into the other
>two inductances.
>
>So, to answer your question on which side of the board to place the
>caps, you need to look at the three inductances of the system.
>
>Regards,
>Larry Smith
>Altera Corporation=3D20
>
>
>
>-----Original Message-----
>From: steve weir [mailto:weirsi@xxxxxxxxxx]=3D20
>Sent: Friday, October 21, 2005 4:11 PM
>To: christopher.mcgrath@xxxxxxxxx; Larry Smith;
>ludovic.levieil@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Power plane coupling
>
>Chris,
>
>You always want to think in terms of minimizing demon inductance. So,
>first=3D20
>we want to put the plane(s) that support our lowest impedance
>requirements=3D20
>closest to the device they feed. Not every plane can be in the top of
>the=3D20
>stack, so this will compromise some supplies.
>
>The placement of capacitors should also be selected to minimize the
>total=3D20
>inductance between the caps and the devices they serve. For a =
plane=3D20
>towards the bottom of the board, this means the caps go on the bottom.
>We=3D20
>are already burned by the long vias from the device to a plane near
the=3D20
>opposite side of the board. If we place the caps on the same side as
>the=3D20
>part, then the attachment vias for the caps will be just as long, a
very
>
>bad thing.
>
>Spreading inductance is another issue. It is part of the price we pay
>for=3D20
>the reality that it is essentially impossible to put discrete caps of
>any=3D20
>size right on the die pads. The further we move away in any axis,
the=3D20
>higher a penalty we pay. The natural log behavior of spreading
>inductance=3D20
>and resistance is such that once we are in for a dime, we might as well
>be=3D20
>in for a dollar.
>
>Regards,
>
>
>Steve.
>At 01:32 PM 10/21/2005 -0700, Mcgrath, Christopher wrote:
> >Larry,
> >
> >I have a related question that popped into my head when I read your
> >response.
> >
> >If you expand this example so that there were a number of layers
>between
> >VCC1 and VCC2 which included both ground and signal layers so that
the
> >thickness of the board begins to become significant with respect to
the
> >placement of decoupling capacitors, is the preferred location for
> >decoupling of a device placed on the top side of the PCB on the top
>side
> >or bottom side of the board IF the voltage being decoupled is VCC2.
> >
> >At issue is whether it is better to place the decoupling capacitor
> >closer to the voltage it is decoupling or closer to the device that
is
> >actually receiving the power.
> >
> >I believe that the path with the least inductance and maximum
> >effectiveness would be to place the decoupling capacitor on the top
>side
> >of the board right next to the device. While the spreading
inductance
> >should be very similar in both cases, the loop inductance would be
> >slightly less when the cap is placed on the top of the board. =3D3D20
> >
> >Any thoughts?
> >
> >Thanks,
> >Chris
> >
> >=3D3D20
> >
> > >-----Original Message-----
> > >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx] On
> > >Behalf Of Larry Smith
> > >Sent: Friday, October 21, 2005 12:05 PM
> > >To: ludovic.levieil@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > >Subject: [SI-LIST] Re: Power plane coupling
> > >
> > >Ludovic - I like this power plane stackup sequence, particularly if
>it
> > >is on the top or bottom surface of the PCB.
> > >
> > >The power planes will be highly coupled to ground by discrete
> >decoupling
> > >capacitors mounted on the surface of the board. There are probably
> > >100's of uF that are trying to maintain a constant voltage between
>VCC1
> > >and Gnd, also between VCC2 and Gnd. But the internal plane to
plane
> > >capacitance is on the order of 1nF, not much compared to the
external
> > >capacitance. At 100MHz, the 1 nF plane-to-plane impedance is about
> > >1/(2*pi*100e+6*1e-9) =3D3D3D3D 1.59 Ohms. This is not strong
compared =3D
>to
>=3D3D
> >the
> > >impedance of the PDS which is probably in the mOhms. The impedance
> > >division insures that there will not be substantial noise coupled
>from
> > >one power plane to the other in this stackup. But as Istvan has
> > >commented in another note on this thread, this might not be best
for
>a
> > >sensitive analog supply or PLL circuitry. Further filtering should
>be
> > >used for those supplies.
> > >
> > >Noise above 100 MHz usually gets onto a power plane because of
> > >transmission line return current. I like your stackup because the
> >power
> > >planes are surrounded by Gnd planes. You have an opportunity for
> > >transmission lines to reference only ground planes throughout the
>rest
> > >of the stackup. This keeps the return current noise off the power
> > >planes and the power plane noise off the transmission lines. Skin
> > >effect in solid ground planes greatly attenuates magnetic fields
from
> > >penetrating through the planes at 1 MHz and above.
> > >
> > >Noise below 100 MHz is usually caused by current transients from
the
> > >loads. A well designed PDS will be below target impedance from
some
> > >corner frequency (50 to 100 MHz) all the way down to DC. The noise
> > >coupled between power planes below this corner frequency is
>diminished
> > >because the impedance of the plane-to-plane capacitance diminishes
at
> > >lower frequency. This stackup puts you well on the way towards
good
> > >power and signal integrity in your product.
> > >
> > >Regards,
> > >Larry Smith
> > >Altera Corporation
> > >(Sun Microsystems was very good for me, but it was time to move
on.)
> > >
> > >-----Original Message-----
> > >From: si-list-bounce@xxxxxxxxxxxxx
> >[mailto:si-list-bounce@xxxxxxxxxxxxx]
> > >On Behalf Of Ludovic Levieil
> > >Sent: Thursday, October 20, 2005 1:12 AM
> > >To: si-list@xxxxxxxxxxxxx
> > >Subject: [SI-LIST] Power plane coupling
> > >
> > >Hello All,
> > >In my current board design I have the following stack up:
> > >
> > > .......
> > >---------------- GND (solid plane)
> > >------ ----- --- VCC1 (splitted plane)
> > >--- ----- ------ VCC2 (splitted plane)
> > >---------------- GND (solid plane)
> > > .......
> > >
> > >4 mils separate GND and VCC planes
> > >5 mils separate VCC1 and VCC2 planes
> > >
> > >Both VCC planes are splitted in different power domains and I am
> > >wondering=3D3D3D20
> > >:
> > > - if having two coupled VCC planes is good/acceptable
>when=3D3D3D20
> > >thinking about noise ??
> > > - if there is a problem in having one power domain on on
> >plane=3D3D3D20
> > >overlapping at least two power domains on the other plane ??
> > >
> > >Thanks
> > >
> > >Ludovic Levieil=3D3D3D20
> > >
> > >------------------------------------------------------------------
> > >To unsubscribe from si-list:
> > >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
field
> > >
> > >or to administer your membership from a web page, go to:
> > >//www.freelists.org/webpage/si-list
> > >
> > >For help:
> > >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > >List FAQ wiki page is located at:
> > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > >
> > >List technical documents are available at:
> > > http://www.si-list.org
> > >
> > >List archives are viewable at: =3D3D3D20
> > > //www.freelists.org/archives/si-list
> > >or at our remote archives:
> > > http://groups.yahoo.com/group/si-list/messages
> > >Old (prior to June 6, 2001) list archives are viewable at:
> > > http://www.qsl.net/wb6tpu
> > > =3D3D3D20
> > >
> > >
> > >
> > >------------------------------------------------------------------
> > >To unsubscribe from si-list:
> > >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
field
> > >
> > >or to administer your membership from a web page, go to:
> > >//www.freelists.org/webpage/si-list
> > >
> > >For help:
> > >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > >List FAQ wiki page is located at:
> > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > >
> > >List technical documents are available at:
> > > http://www.si-list.org
> > >
> > >List archives are viewable at:
> > > //www.freelists.org/archives/si-list
> > >or at our remote archives:
> > > http://groups.yahoo.com/group/si-list/messages
> > >Old (prior to June 6, 2001) list archives are viewable at:
> > > http://www.qsl.net/wb6tpu
> > >
> >
> >------------------------------------------------------------------
> >To unsubscribe from si-list:
> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> >or to administer your membership from a web page, go to:
> >//www.freelists.org/webpage/si-list
> >
> >For help:
> >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> >List FAQ wiki page is located at:
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> >
> >List technical documents are available at:
> > http://www.si-list.org
> >
> >List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> >Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
>
>
>
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>//www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
> http://www.si-list.org
>
>List archives are viewable at:
> //www.freelists.org/archives/si-list
>or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
