[SI-LIST] Re: Power Integrity about Vtt of DDR
- From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- To: zhang_kun@xxxxxxxxxx
- Date: Fri, 14 May 2004 08:37:16 -0700
Zhangkun
All of your DDR DQS, DQ, and DM signals should be routed overtop of a
ground plane. This reduces return path effects in the package and connector.
Both VDD and VTT should be as small a plane or fill area as possible, to
reduce planar resonance effects. For VTT termination resistors, use 8
pin 4 resistors R-paks. Place an outer layer Vtt fill area behind the
resistors and for each Rpak use 1 0603 0.1 uF ceramic capacitor directly
behind the resistor. This will insure ample decoupling for VTT. For
Vdd decoupling you will need to compute the worst case instantaneous
current required by your devices and the acceptable noise level,
(usually 5%) and from that compute the necessary ESL to accomplish
this. Based on the ESL you will then select the number of 0.1 uF
capacitors to meet your ESL needs by calculating (or solving for) the
mounted inductance of the capacitor, and computing the number in
parallel necessary to meet your requirement.
regards,
scott
Zhangkun wrote:
>Dear all:
>In DDR, there are two power, VDD and VTT. For example, VDD=2.5V and VTT=1.25V.
>VDD should be decoupled very well. How about the decoupling of VTT? Is it
>important? How to arrange the VDD, VTT and GND?
>
>Best Regards
>
>Zhangkun
>2004.5.14
>
>
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--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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Teraspeed Consulting Group LLC
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