[SI-LIST] Re: Power Integrity about Vtt of DDR
- From: Dav0 Lieby <dav0x@xxxxxxxxx>
- To: SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 17 May 2004 08:34:56 -0700 (PDT)
Hi,
As long as the signals coming to the connector
for the DIMM are referenced to the same VTT, you
would be OK. If the mother board signals are
referenced to ground, and you change on the DIMM
to VTT, you will need to couple the currents to
VTT from Ground.
That is a can of worms. Perhaps better, if you
do not have control of the mother board, to keep
the signals referenced to ground.
dav0
David Lieby
Siemens Medical Solutions, Ultrasound Division
Mountain View
--- hermann.ruckerbauer@xxxxxxxxxxxx wrote:
> Subject: [SI-LIST] AW: Re: Power Integrity about Vtt
> of DDR
> Date: Mon, 17 May 2004 09:00:27 +0200
> From: <hermann.ruckerbauer@xxxxxxxxxxxx>
> To: <zhang_kun@xxxxxxxxxx>, <scott@xxxxxxxxxxxxx>,
> <si-list@xxxxxxxxxxxxx>
>
> Hello,
>
> just a short comment regarding referencing ...
>
> On DDR2 DIMM modules and Connector pinout CCA
> signals (Control, comand, =
> address) are referenced to VDD.
> So it might make sense to keep this referencing, or
> at least do some low =
> ESL short at the
> break point of reference.
>
> For DDR1 referencing all to VSS is best as Scott
> mentioned!
>
>
> Hermann
>
> -----Urspr=FCngliche Nachricht-----
> Von: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] =
> Im Auftrag von Zhangkun
> Gesendet: Montag, 17. Mai 2004 03:03
> An: scott@xxxxxxxxxxxxx; silist
> Betreff: [SI-LIST] Re: Power Integrity about Vtt of
> DDR
>
>
> Dear Scott
>
> Is there some document about the decoupling of power
> of DDR?
>
> Best Regards
>
> Zhangkun
> 2004.5.17
> ----- Original Message -----=20
> From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
> To: "Zhangkun" <zhang_kun@xxxxxxxxxx>; "silist"
> <si-list@xxxxxxxxxxxxx>
> Sent: Monday, May 17, 2004 12:15 AM
> Subject: [SI-LIST] Re: Power Integrity about Vtt of
> DDR
>
>
> > Zhangkun,
> > If you keep all the DQ, DQS and DM signals
> referenced to a ground=20
> > plane,
> > there will be no power injection into the Vdd
> power/ground plates at =
> DDR=20
> > switching frequency. (It is always preferable to
> have all DDR signals=20
> > referenced to a ground plane, including Address
> and Control. But if =
> you=20
> > have a choice, at least reference the data rate
> signals, as they have=20
> > the highest harmonic content.) This reduces high
> frequency noise on =
> the=20
> > VDD plane. What is left is the mid-frequency core
> power noise and=20
> > address/control switching noise which extends up
> to a hundred MHz or=20
> > so. This can be adequeately decoupled by
> capacitors with the=20
> > appropriate consideration of ESL. If you use
> large Vdd/gnd planes, =
> you=20
> > run the risk of driving the resonant frequency of
> these planes down to =
>
> > one of the lower harmonics of the core or I/O
> switching clocks. Then=20
> > you will need to decouple these resonances with an
> excess of =
> capacitance=20
> > to counter the anti-resonance peaks formed between
> the plane and the=20
> > capacitors.
> >=20
> > In general, large planes do little to help
> matters. You receive the
> > most benefit first from referencing signals to
> ground and second from=20
> > thin power/ground pairs. Large planes can
> oftentimes make matters=20
> > worse. I realize this sounds like heresy, but it
> is very true. The=20
> > problem then becomes in navigating around the
> plane splits or fill=20
> > areas, embedding your power fill areas between
> several ground planes =
> on=20
> > thick multi-layer boards, and choosing the
> appropriate position in =
> the=20
> > board stackup to reduce the overall mounted
> capacitor inductance for =
> the=20
> > power layers.
> >=20
> > For Vtt, in specific, a fill area on the surface
> of the board, with an
> > adjacent ground plane underneath, which just
> encompases all of the=20
> > terminators and capacitors, is extremely
> efficient. Since one pad of =
>
> > the capacitor is connected directly to the Vtt
> fill, and the other pad =
>
> > uses vias dropped to the underlying ground plane
> several mils away, =
> the=20
> > mounted inductance is extremely low, and
> approaches the inductance of=20
> > the capacitor body, itself. You can make the
> plane large if you want, =
>
> > to lower the Vdd fill area impedance, but do not
> make it so large that =
> a=20
> > resonance is excited that will "sing" with the
> capacitors. You would=20
> > like to keep the resonant frequency of the plane
> above at least 3X to =
> 4X=20
> > the switching freqency. For DDR 400, the
> switching frequency is 200=20
> > MHz. As such, keep the plane resonance above 600
> to 800 MHz for best=20
> > performance. This dictates a maximum dimension of
> around 3.5 to 5=20
> > inches on FR4 laminates. (Resonant frequency of a
> 5" cavity in FR4 =
> @170=20
> > ps/in is 1/(5*170e-12 *2), for the half-wave
> resonant point.)
> >=20
> > regards,
> >=20
> > scott
> >=20
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 2926 SE Yamhill St.
> > Portland, OR 97214
> > (503) 239-5536
> > http://www.teraspeed.com
> >=20
> > Teraspeed is the registered service mark of
> > Teraspeed Consulting Group LLC
> >=20
> >=20
> >=20
> > Zhangkun wrote:
> >=20
> > >Dear Scott
> > >
> > >"Both VDD and VTT should be as small a plane or
> fill area as=20
> > >possible, to reduce planar resonance effects."
> > >
> > >I donot agree with this point. When the plane is
> small, the=20
> > >plane-capacitance is small. At high frequency
> domain, the=20
> > >plane-capacitance is the most important for
> decoupling.
> > >
> > >Best Regards
> > >
> > >Zhangkun
> > >2004.5.16
> > >----- Original Message -----
> > >From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
> > >To: <zhang_kun@xxxxxxxxxx>
> > >Cc: "si-list" <si-list@xxxxxxxxxxxxx>
> > >Sent: Friday, May 14, 2004 11:37 PM
> > >Subject: [SI-LIST] Re: Power Integrity about Vtt
> of DDR
> > >
> > >
> > > =20
> > >
> > >>Zhangkun
> > >>
> > >>All of your DDR DQS, DQ, and DM signals should
> be routed overtop of=20
> > >>a
> > >>ground plane. This reduces return path effects
> in the package and =
> connector.
> > >>
> > >>Both VDD and VTT should be as small a plane or
> fill area as=20
> > >>possible, to
> > >>reduce planar resonance effects. For VTT
> termination resistors, use =
> 8=20
> > >>pin 4 resistors R-paks. Place an outer layer
> Vtt fill area behind =
> the=20
> > >>resistors and for each Rpak use 1 0603 0.1 uF
> ceramic capacitor =
> directly=20
> > >>behind the resistor. This will insure ample
> decoupling for VTT. =
> For=20
> > >>Vdd decoupling you will need to compute the
> worst case instantaneous =
>
> > >>current required by your devices and the
> acceptable noise level,=20
> > >>(usually 5%) and from that compute the necessary
> ESL to accomplish=20
> > >>this. Based on the ESL you will then select the
> number of 0.1 uF=20
> > >>capacitors to meet your ESL needs by calculating
> (or solving for) =
> the=20
> > >>mounted inductance of the capacitor, and
> computing the number in=20
> > >>parallel necessary to meet your requirement.
> > >>
> > >>regards,
> > >>
> > >>scott
> > >>
> > >>
> > >>Zhangkun wrote:
> > >>
> > >> =20
> > >>
> > >>>Dear all:
> > >>>In DDR, there are two power, VDD and VTT. For
> example, VDD=3D2.5V =
> and=20
> > >>>VTT=3D1.25V. VDD should be decoupled very well.
> How about the=20
> > >>>decoupling of VTT? Is it important? How to
> arrange the VDD, VTT and =
>
> > >>>GND?
> > >>>
> > >>>Best Regards
> > >>>
> > >>>Zhangkun
> > >>>2004.5.14
> > >>>
> > >>>
> >
>
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> > >>--
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> > >>Scott McMorrow
> > >>Teraspeed Consulting Group LLC
> > >>2926 SE Yamhill St.
> > >>Portland, OR 97214
> > >>(503) 239-5536
> > >>http://www.teraspeed.com
> > >>
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> > --
> >=20
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 2926 SE Yamhill St.
> > Portland, OR 97214
> > (503) 239-5536
> > http://www.teraspeed.com
> >=20
> > Teraspeed is the registered service mark of
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