[SI-LIST] Re: Power Integrity about Vtt of DDR

Dear Scott

Is there some document about the decoupling of power of DDR?

Best Regards

Zhangkun
2004.5.17
----- Original Message ----- 
From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
To: "Zhangkun" <zhang_kun@xxxxxxxxxx>; "silist" <si-list@xxxxxxxxxxxxx>
Sent: Monday, May 17, 2004 12:15 AM
Subject: [SI-LIST] Re: Power Integrity about Vtt of DDR


> Zhangkun,
> If you keep all the DQ, DQS and DM signals referenced to a ground plane, 
> there will be no power injection into the Vdd power/ground plates at DDR 
> switching frequency. (It is always preferable to have all DDR signals 
> referenced to a ground plane, including Address and Control.  But if you 
> have a choice, at least reference the data rate signals, as they have 
> the highest harmonic content.)  This reduces high frequency noise on the 
> VDD plane. What is left is the mid-frequency core power noise and 
> address/control switching noise which extends up to a hundred MHz or 
> so.  This can be adequeately decoupled by capacitors with the 
> appropriate consideration of ESL.  If you use large Vdd/gnd planes, you 
> run the risk of driving the resonant frequency of these planes down to 
> one of the lower harmonics of the core or I/O switching clocks.  Then 
> you will need to decouple these resonances with an excess of capacitance 
> to counter the anti-resonance peaks formed between the plane and the 
> capacitors.
> 
> In general, large planes do little to help matters.  You receive the 
> most benefit first from referencing signals to ground and second from 
> thin power/ground pairs. Large planes can oftentimes make matters 
> worse.  I realize this sounds like heresy, but it is very true.  The 
> problem then becomes in navigating around the plane splits or fill 
> areas,  embedding your power fill areas between several ground planes on 
> thick multi-layer boards,  and choosing the appropriate position in the 
> board stackup to reduce the overall mounted capacitor inductance for the 
> power layers.
> 
> For Vtt, in specific, a fill area on the surface of the board, with an 
> adjacent ground plane underneath,  which just encompases all of the 
> terminators and capacitors,  is extremely efficient.  Since one pad of 
> the capacitor is connected directly to the Vtt fill, and the other pad 
> uses vias dropped to the underlying ground plane several mils away, the 
> mounted inductance is extremely low, and approaches the inductance of 
> the capacitor body, itself.  You can make the plane large if you want, 
> to lower the Vdd fill area impedance, but do not make it so large that a 
> resonance is excited that will "sing" with the capacitors.  You would 
> like to keep the resonant frequency of the plane above at least 3X to 4X 
> the switching freqency.  For DDR 400, the switching frequency is 200 
> MHz.  As such, keep the plane resonance above 600 to 800 MHz for best 
> performance.  This dictates a maximum dimension of around 3.5 to 5 
> inches on FR4 laminates.  (Resonant frequency of a 5" cavity in FR4 @170 
> ps/in  is 1/(5*170e-12 *2), for the half-wave resonant point.)
> 
> regards,
> 
> scott
> 
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
> 
> Teraspeed is the registered service mark of 
> Teraspeed Consulting Group LLC
> 
> 
> 
> Zhangkun wrote:
> 
> >Dear Scott
> >
> >"Both VDD and VTT should be as small a plane or fill area as possible, to 
> >reduce planar resonance effects."
> >
> >I donot agree with this point. When the plane is small, the 
> >plane-capacitance is small. At high frequency domain, the plane-capacitance 
> >is the most important for decoupling.
> >
> >Best Regards
> >
> >Zhangkun
> >2004.5.16
> >----- Original Message ----- 
> >From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
> >To: <zhang_kun@xxxxxxxxxx>
> >Cc: "si-list" <si-list@xxxxxxxxxxxxx>
> >Sent: Friday, May 14, 2004 11:37 PM
> >Subject: [SI-LIST] Re: Power Integrity about Vtt of DDR
> >
> >
> >  
> >
> >>Zhangkun
> >>
> >>All of your DDR DQS, DQ, and DM signals should be routed overtop of a 
> >>ground plane. This reduces return path effects in the package and connector.
> >>
> >>Both VDD and VTT should be as small a plane or fill area as possible, to 
> >>reduce planar resonance effects.  For VTT termination resistors, use 8 
> >>pin 4 resistors R-paks.  Place an outer layer Vtt fill area behind the 
> >>resistors and for each Rpak use 1 0603 0.1 uF ceramic capacitor directly 
> >>behind the resistor.  This will insure ample decoupling for VTT.  For 
> >>Vdd decoupling you will need to compute the worst case instantaneous 
> >>current required by your devices and the acceptable noise level, 
> >>(usually 5%) and from that compute the necessary ESL to accomplish 
> >>this.  Based on the ESL you will then select the number of 0.1 uF 
> >>capacitors to meet your ESL needs by calculating (or solving for) the 
> >>mounted inductance of the capacitor, and computing the number in 
> >>parallel necessary to meet your requirement.
> >>
> >>regards,
> >>
> >>scott
> >>
> >>
> >>Zhangkun wrote:
> >>
> >>    
> >>
> >>>Dear all:
> >>>In DDR, there are two power, VDD and VTT. For example, VDD=2.5V and 
> >>>VTT=1.25V. VDD should be decoupled very well. How about the decoupling of 
> >>>VTT? Is it important? How to arrange the VDD, VTT and GND?
> >>>
> >>>Best Regards
> >>>
> >>>Zhangkun
> >>>2004.5.14
> >>>
> >>>
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> >>-- 
> >>
> >>Scott McMorrow
> >>Teraspeed Consulting Group LLC
> >>2926 SE Yamhill St.
> >>Portland, OR 97214
> >>(503) 239-5536
> >>http://www.teraspeed.com
> >>
> >>Teraspeed is the registered service mark of 
> >>Teraspeed Consulting Group LLC
> >>
> >>
> >>
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> >
> >  
> >
> 
> -- 
> 
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
> 
> Teraspeed is the registered service mark of 
> Teraspeed Consulting Group LLC
> 
> 
> 
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