[SI-LIST] Re: Newbie board question

Hi Glen,

based on my experience with working with Virtex-IIs, and big ones
at that, you will have no problem, provided the speed grade is
right, etc.

I have worked on lots of boards featuring the 1152 and 1517 pin
package versions, and on all systems, we get core clocks running
at 200 MHz, no problem - even a big 11 board system, with 18 of
the 1517 pin BGAs, devouring around 300W in a housing around the
size of a briefcase. EMC was also fine 1st time - something we had
hoped for, building on past experience, but what was nevertheless
a pleasant surprise, considering just what is going on!

I didn't use micro- or blind vias to realise these designs, and
still decoupled the FPGAs with lots of 0402 caps (100nF) under
the centre on the bottom, which fit perfectly between small, normal
vias, coupled with an array of Tants around the outside of the BGA.
With a smaller BGA package this will still be possible, just there
will be fewer caps (but then the decoupling requirements are lower).

I would also go with pretty much everything Steve said, particularly
the layer ordering - outer layer track impedances will vary more
than inner layers: the outer copper will be plated (how thick the
plating is, depends upon the density of the circuitry/routing in the
vicinity), whereas the inner layers are not plated. This effect can
be reduced with extra work, but use the inner layers, and you avoid
the effort completely.
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax:   +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________=20



-----Urspr=FCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
Im Auftrag von Glenn Judd
Gesendet: Freitag, 14. Mai 2004 06:54
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Newbie board question



(As this is a newbie question; apologies to those not
interested.)

Hi All,

I have a nearly complete beta design of a high
speed board. I've tried to follow principles
gleaned from this list and other sources,
but since my background is in CS (no grumbling=3D20
please :) ), I thought it would be prudent to=3D20
run my design past any altruistic readers here=3D20
just to see if there are any obvious high level=3D20
issues that I should be concerned with.

Goal

FPGA (Virtex-II) based signal processing board=3D20
w/ core clock running @ 200 MHz. Basic signal=3D20
is 12 bits @ 200 Msps. This is for academic=3D20
research, so I'm more worried about correctness=3D20
and low number of spins than I am about optimizing=3D20
component cost etc.

I/O

Input1:  12 bits LVDS @ 200 MHz
Output1: 2x12 bits CMOS @ 100 MHz (interleaving gives=3D20
         basic signal)
(these I/Os will eventually be an intra-board signal,=3D20
inter-board in prototype)
        =3D20
Input2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
Output2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
(these I/Os are running inter-board over LVDS/SCSI cable
w/ VHDCI connectors)

Stackup

Layer   Type   Separation (mils)
1       LVDS
               8
2       GND
               8
3       VCC 1.5 (powers FPGA core)
               4.5
4       VCC 2.5 (powers LVDS)
               8
5       CMOS (flooded w/ GND where possible)
               4.5
6       VCC 3.3 (powers CMOS)
               8
7       GND
               8
8       LVDS

outer copper 1 ounce, inner 0.5 ounce

Decoupling Caps
I have over 1 cap/power pin since I'm
trying to err on the side of caution.

(Not showing caps near/required by voltage=3D20
regulators)
VCC
1.5  2.5  3.3   Capacitor (uf)
------------------------------
 4*  10*   4*    0.0022=3D09
 4*   6    6     0.022
 2    6    2     0.1
 2    2    2     1
 1    1    1     4.7
 1    1    1    47
* =3D3D located under FPGA in middle of ball grid

I'm using blind vias on the FPGA's center ground pins
to create room underneath. This requires blind
vias in two directions though (top for FPGA GND,=3D20
bottom caps fanout). Naturally if I could get by=3D20
with no-blind vias and only a couple caps directly=3D20
under, that would be great. Since I really don't
know if that's OK or not, I'm erring on the side of=3D20
caution; I'd rather have a more expensive initial=3D20
spin than a respin/power plane debug.

Traces

Used National's app notes for LVDS to determine differential
pair spacing etc. LVDS trace sep is 5 mils. I'm using guard
traces for all high speed signals (not sure if necessary...).

Banking

I've split the interleaved 12-bit 100 MHz CMOS signals
across two IO banks each so that each bank always has
6 (potential) changing IOs. I'm hoping to reduce
simultaneous switching IOs and ground bounce issues here.

Design Success Criteria

core clock speed
200 MHz =3D3D ideal
150 MHz =3D3D near ideal
100 MHz =3D3D fair
50 MHz =3D3D semi-functional
< =3D3D expensive toy

Again, I'm looking for high-level comments (even
"you'll never succeed" would be OK :) ) and not
expecting a detailed critique.

Thanks in advance!

Glenn


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