[SI-LIST] Re: High speed signals go across isolation moat
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Jack Olson <pcbjack@xxxxxxxxx>
- Date: Wed, 14 Nov 2007 08:03:34 -0800
Jack, propagating fields are remarkably brain dead. They just keep
expanding until they hit metal. When they do, they penetrate a little,
but mostly they reflect. As the field propagates it doesn't know that
there is a break ahead. The wavefront reacts to the break when it hits
it. Since the break represents a big change in the relative impedance,
the energy redistributes, exciting the slot, and draining power from the
forward propagating signal.
Steve.
Jack Olson wrote:
> I can't resist asking a "newbie" question about your statement.
>
> Why would half of the energy couple to the broken-up plane,
> when it could couple to a beautiful solid continous conductive
> surface just to the other side?
> Won't a field form in the "space" of least impedance?
> Is it because the frequency is too high?
>
> Don't answer if its too lame-brained to bother with, ok?
> (One of these days I'm gonna "read up" on this stuff... sorry)
>
> Jack (aka "the new guy")
>
>
> On 11/14/07, *steve weir* <weirsi@xxxxxxxxxx
> <mailto:weirsi@xxxxxxxxxx>> wrote:
>
> Zhuyongfa, yes layer 4 acts as a reflection plane to layer 3 signals.
> Your current stack-up is a nearly symmetric stripline. About half
> the
> energy will be bound between traces on layer 3 and each of the plane
> layers 2, and 4. Where single ended or in-phase differential signals
> cross moats on layer 4, energy will go into exciting the
> slots. Signal
> rise-time, crosstalk, and EMI will all be affected. To know the exact
> extent, you would need to simulate.
>
> You can fix this by adjusting the stack-up to reduce coupling from
> layer
> 3 signals to layer 4 etch by moving layer 3 closer to layer 2, and
> further from layer 4. Do the same thing with layer 8 wrt layers 9 and
> 7. If you use 4 / 11 in place of your current 7 / 8 you will remove
> almost all of the coupling from layer 3 to layer 4.
>
> Good luck.
>
> Steve.
>
> z46147 wrote:
> > Content-type: text/plain; charset=gb2312
> > Content-transfer-encoding: 7BIT
> > Hi all,
> >
> > A ten layers high speed PCB, the second layer is GND, the third
> layer is signal, the fourth is Power layer.
> >
> > GND plane is a full one, never been splited. Several types of
> voltage are on the power layer, so the power layer is isolated by
> so many moats.
> >
> > Thickness between the second and third layer is 7 mil, while 8
> mil between the third and fourth layer.
> >
> > Some high speed signals traces are routed on the third layer,
> such as PCI Express and SAS/SATA signals.
> >
> > If the high speed signal traces go across isolation moat of the
> fourth power layer, can it be treated as crossing split reference
> plane and give rise to signal integrity problem?
> >
> > If it will give rise to signal integrity problem, can we use
> stiching capacitors across isolation moats of the power layer to
> deal with this issue, while changing the
> > isolation moats?
> >
> > Any thought on this issue would be appreciated.
> >
> > Best regards.
> >
> >
> > Zhuyongfa
> > HUAWEI TECHNOLOGIES CO.,LTD.
> >
> >
> > Address: Huawei Industrial Base
> > Bantian Longgang
> > Shenzhen 518129, P.R.China
> > Tel:+86-755-89653025
> > Fax: +86-755-89650731
> > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> > www.huawei.com <http://www.huawei.com>
> >
>
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> --
> Steve Weir
> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
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(707) 780-1951 Fax
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http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
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