[SI-LIST] Re: High speed signals go across isolation moat
- From: wolfgang.maichen@xxxxxxxxxxxx
- To: Jory McKinley <jory_mckinley@xxxxxxxxx>
- Date: Thu, 15 Nov 2007 20:45:42 -0800
Hello Jory,
I fully agree. As for crossing the moat, common mode components on the
differential signal (mismatched rise/fall times being one possible source)
have exactly the same problems as single ended signals. Also, in my
current job I usually have the luxury to disregard EMI issues as long as
the signal integrity is ok otherwise, but common mode will cause EMI
problems as well in the present example.
Wolfgang
Jory McKinley <jory_mckinley@xxxxxxxxx>
11/15/2007 03:28 PM
To
wolfgang.maichen@xxxxxxxxxxxx
cc
si-list@xxxxxxxxxxxxx
Subject
Re: [SI-LIST] Re: High speed signals go across isolation moat
Hello Wolfgang,
Chiming in late on this one and agree with most of comments. Would like
to add in your example that in the differential case imbalanced rise/fall
times create common mode currents which do not cancel and this could be an
issue in the split plane case (if the image reference is the power plane).
-Jory
----- Original Message ----
From: "wolfgang.maichen@xxxxxxxxxxxx" <wolfgang.maichen@xxxxxxxxxxxx>
To: Zhengrong.Xu@xxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx;
weirsi@xxxxxxxxxx; zhuyongfa@xxxxxxxxxx
Sent: Thursday, November 15, 2007 4:58:01 PM
Subject: [SI-LIST] Re: High speed signals go across isolation moat
Hello,
one very important information that hasn't been mentioned so far (or that
I have missed?) is whether the signals crossing the moat ar single ended
lines or differential lines.
- Single ended lines will have a big issue with this arrangement, i.e. you
will see a large inductive discontunity due to half of the return current
being reflected at the boundary. Stitching caps can alleviate the issue,
but will still leave significant reflections - you'll need vias to connect
the capacitors to the power planes, and getting via inductance + mounting
inductance + package inductance low enough is a challenge. As a rough rule
of thumb, about 1nH is as good as you can get... pretty substantial with
rise times in the sub-100ps-range. Putting the next power/gnd layer as
close as possible to the broken power layer will help quite a bit because
it adds some very-low-inductance distributed capacitance that can take
care of the high end of the frequency range.
- Differential lines shouldn't see much of an impact at all. In a naive
picture (that nevertheless produces the right answer), you can simply
think of the two return currents (below true line and below complement
line) canceling ("turning around") on one side of the moat, and then
building up again on the other side. Some time ago I simulated such a case
(with a planar 2.5D field solver) and found the residual parasitic
(because of the additional return path between the two traces) to be
surprisingly small, even with differential pairs that were almost
uncoupled (pair spacing of several line width). I saw only small fractions
of a nH at worst. Measurements on a small experimental test board
confirmed the simulation results. Trace widths were around 8 mils and gap
width in the power plane around 10 mils, but the results were not very
sensitive to those parameters (meaning the parasitics were always small).
You can further improve the situation by about a factor of 2 - 3 by
placing the next plane very close (e.g. 2 mil dielectric) to the broken
plane. Stitching caps do not yield any visible improvement because as I
said above their mounting inductance is too large to make them effective.
That behavior of differential lines is also responsible for the fact that
you can launch a differential signal coming from loosely coupled PCB
traces into a ground-less twisted pair cable.
Hope that helps you in your decision.
Wolfgang
xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>
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11/15/2007 02:23 AM
Please respond to
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Subject
[SI-LIST] Re: High speed signals go across isolation moat
Hi Zhuyongfa,
Steve's suggestion also gives me a new idea about stack-up. Signal =
integrity
benefits from that every signal layer is close to integral reference GND =
and
the PDNs aren't excited by signals, for litte return current on the =
Power
patches. But transient noise on power patches from I/O switching is
unavoidable. So it is necessary for you to have a good decoupling PDNs =
so
that ripple on PDNs is small enough to have EMI problems. Paving GND =
copper
on both surfaces is also beneficial for EMI.
Moreover, you said, " Most of the gap width in the power plane is 30 =
mil, it
seems that we had better reduce it to 20 mil."
I think, we use splitting plane for insulating deferent voltage patches. =
The
gap width lies on the difference of voltages. For the purpose of signal
integrity, maybe it is better to reduce the gap width to increase the
capacitive coupling, but it will increase the noise coupling between
different patches at the same time. It is a trade-off. So you'd better =
give
an close integral GND for high speed signals. If not met, add stitching
capacitor or partly reducing the gap width beneath the signal should be
judged by field simulation.
Best Regards
Zhengrong
-----=D3=CA=BC=FE=D4=AD=BC=FE-----
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[mailto:si-list-bounce@xxxxxxxxxxxxx]
=B4=FA=B1=ED z46147
=B7=A2=CB=CD=CA=B1=BC=E4: 2007=C4=EA11=D4=C215=C8=D5 16:13
=CA=D5=BC=FE=C8=CB: steve weir
=B3=AD=CB=CD: si-list@xxxxxxxxxxxxx; duyumin@xxxxxxxxxx; =
xiaoji@xxxxxxxxxx
=D6=F7=CC=E2: [SI-LIST] Re: High speed signals go across isolation moat
Content-type: text/plain; charset=3Diso-8859-1
Content-transfer-encoding: 7BIT
Steve,
It is a good suggestion, but you know we have never tried the stack-up
before.
We always use a solid GND plane just underneath the devices(it means =
layer 2
of any board must be GND plane).
Maybe we can try it.
Zhuyongfa
HUAWEI TECHNOLOGIES CO.,LTD. =20
Address: Huawei Industrial Base
Bantian Longgang
Shenzhen 518129, P.R.China
Tel:+86-755-89653025=20
Fax: +86-755-89650731
E-mail: zhuyongfa@xxxxxxxxxx
www.huawei.com
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This e-mail and its attachments contain confidential information from
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Any
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----- Original Message -----=20
From: steve weir=20
To: z46147=20
Cc: si-list@xxxxxxxxxxxxx ; duyumin@xxxxxxxxxx ; xiaoji@xxxxxxxxxx=20
Sent: Thursday, November 15, 2007 2:53 PM
Subject: Re: [SI-LIST] Re: High speed signals go across isolation moat
Zhuyongfa, a shield is often a patch applied to fix another problem. =
In=20
the case of the earlier stack-up the PDN patches are strongly excited =
by=20
signals on all of the internal routing layers, save layer 6. =
Transitions=20
to / from any of the layers 3, 5, or 8 to / from layer 6 will also=20
excite the PDN patches and all that connects to them, including the=20
components on the top of the board, and any signals that go in and out =
of the box.
The proposed stack-up gets rid of those problems by eliminating the=20
signal coupling to the PDN patches. All the internal routing layers: =
3,=20
5, 6, and 8 reference GND alone and do not excite the PDNs. There is=20
still some cavity excitation, but this is readily dealt with by common =
measures as in adequate stitch via density particularly near the board =
edges.
As an analogy: If you want peace and quiet you can either put lots of=20
insulation between your apartment and your neighbors. But any open=20
window will still be a problem. If instead you live next to quiet=20
neighbors you can enjoy both the quiet and an open window.
Steve.
z46147 wrote:
> Steve,
> According to your suggestion, layer 2 and layer 9 are PWR planes, I=20
> think it is not good for EMI performance.
> Defining one or more GND plane outer will have good shield effect.
> Any thought would be appreciated.
> Regards.
> Zhuyongfa
> HUAWEI TECHNOLOGIES CO.,LTD. huawei_logo
> Address: Huawei Industrial Base
> Bantian Longgang
> Shenzhen 518129, P.R.China
> Tel:+86-755-89653025
> Fax: +86-755-89650731
> E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> www.huawei.com <http://www.huawei.com>
>
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> ----- Original Message -----
> *From:* steve weir <mailto:weirsi@xxxxxxxxxx>
> *To:* z46147 <mailto:zhuyongfa@xxxxxxxxxx>
> *Cc:* si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx> ;
> duyumin@xxxxxxxxxx <mailto:duyumin@xxxxxxxxxx> ; =
xiaoji@xxxxxxxxxx
> <mailto:xiaoji@xxxxxxxxxx>
> *Sent:* Thursday, November 15, 2007 12:24 PM
> *Subject:* [SI-LIST] Re: High speed signals go across isolation =
moat
>
> Zhuyongfa well that makes the problem more complicated. So what =
we
> know
> about the stack-up:
>
> 1 Top
> 2 GND
> 7mils
> 3 Signal
> 8 mils
> 4 Power mixed
> 5 ? presume signal
> 6 ? presume signal
> 7 GND
> 8 mils
> 8 ? presume signal
> 7 mils
> 9 Power mixed
> 10 Bottom
>
> I suggest that this would work better:
>
> 1 Top
> 2 Power mixed
> 11
> 3 Signal
> 4 mils
> 4 GND
> 4 mils
> 5 signal
> > 10 mils
> 6 signal
> 4 mils
> 7 GND
> 4 mils
> 8 signal
> 11 mils
> 9 Power mixed
> 10 Bottom
>
> All signal layers tightly reference GND, can readily change =
routing
> layers as needed and will perform well. The distance from GND to
> any of
> the power layers hasn't changed so your bypass for IC power
> delivery is
> unchanged. But now the signals will not excite the PDN, making =
the
> board
> much quieter for a given bypass strategy.
>
> Steve.
>
> z46147 wrote:
> > Steve,
> > Adjusting the stack-up is not a good choice.
> > Cause layer 2 and layer 7 are solid GND planes, and layer 4 =
and
> layer
> > 9 are power planes.
> > If we move layer 3 close to layer 2, then layer 9 will be =
close to
> > layer 8 too. Then high speed signal traces on layer 8 will go
> across
> > isolation moats on layer 9.
> > Thanks and regards.
> > Zhuyongfa
> > HUAWEI TECHNOLOGIES CO.,LTD. huawei_logo
> >
> > Address: Huawei Industrial Base
> > Bantian Longgang
> > Shenzhen 518129, P.R.China
> > Tel:+86-755-89653025
> > Fax: +86-755-89650731
> > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> <mailto:zhuyongfa@xxxxxxxxxx>
> > www.huawei.com <http://www.huawei.com> <http://www.huawei.com>
> >
>
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> > above. Any use of the
> > information contained herein in any way (including, but not
limited
> > to, total or partial
> > disclosure, reproduction, or dissemination) by persons other
> than the
> > intended
> > recipient(s) is prohibited. If you receive this e-mail in =
error,
> > please notify the sender by
> > phone or email immediately and delete it!
> >
> > ----- Original Message -----
> > *From:* steve weir <mailto:weirsi@xxxxxxxxxx>
> > *To:* zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> <mailto:zhuyongfa@xxxxxxxxxx>
> > *Cc:* si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
> <mailto:si-list@xxxxxxxxxxxxx> ;
> > duyumin@xxxxxxxxxx <mailto:duyumin@xxxxxxxxxx>
> <mailto:duyumin@xxxxxxxxxx> ; xiaoji@xxxxxxxxxx
> <mailto:xiaoji@xxxxxxxxxx>
> > <mailto:xiaoji@xxxxxxxxxx>
> > *Sent:* Wednesday, November 14, 2007 6:31 PM
> > *Subject:* Re: [SI-LIST] High speed signals go across =
isolation
moat
> >
> > Zhuyongfa, yes layer 4 acts as a reflection plane to layer 3
> signals.
> > Your current stack-up is a nearly symmetric stripline. About
> half the
> > energy will be bound between traces on layer 3 and each of the
plane
> > layers 2, and 4. Where single ended or in-phase differential
signals
> > cross moats on layer 4, energy will go into exciting the =
slots.
> > Signal
> > rise-time, crosstalk, and EMI will all be affected. To know =
the
> exact
> > extent, you would need to simulate.
> >
> > You can fix this by adjusting the stack-up to reduce coupling =
from
> > layer
> > 3 signals to layer 4 etch by moving layer 3 closer to layer 2, =
and
> > further from layer 4. Do the same thing with layer 8 wrt =
layers
> 9 and
> > 7. If you use 4 / 11 in place of your current 7 / 8 you will
remove
> > almost all of the coupling from layer 3 to layer 4.
> >
> > Good luck.
> >
> > Steve.
> >
> > z46147 wrote:
> > > Content-type: text/plain; charset=3Dgb2312
> > > Content-transfer-encoding: 7BIT
> > > Hi all,
> > >
> > > A ten layers high speed PCB, the second layer is GND, the =
third
> > layer is signal, the fourth is Power layer.
> > >
> > > GND plane is a full one, never been splited. Several types =
of
> > voltage are on the power layer, so the power layer is isolated =
by
> > so many moats.
> > >
> > > Thickness between the second and third layer is 7 mil, while =
8
> > mil between the third and fourth layer.
> > >
> > > Some high speed signals traces are routed on the third =
layer,
> > such as PCI Express and SAS/SATA signals.
> > >
> > > If the high speed signal traces go across isolation moat of =
the
> > fourth power layer, can it be treated as crossing split =
reference
> > plane and give rise to signal integrity problem?
> > >
> > > If it will give rise to signal integrity problem, can we use
> > stiching capacitors across isolation moats of the power layer =
to
> > deal with this issue, while changing the
> > > isolation moats?
> > >
> > > Any thought on this issue would be appreciated.
> > >
> > > Best regards.
> > >
> > >
> > > Zhuyongfa
> > > HUAWEI TECHNOLOGIES CO.,LTD.
> > >
> > >
> > > Address: Huawei Industrial Base
> > > Bantian Longgang
> > > Shenzhen 518129, P.R.China
> > > Tel:+86-755-89653025
> > > Fax: +86-755-89650731
> > > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> <mailto:zhuyongfa@xxxxxxxxxx>
> > > www.huawei.com <http://www.huawei.com> =
<http://www.huawei.com>
> > >
> >
>
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