[SI-LIST] Re: High speed signals go across isolation moat

Steve is correct only when the system is completely symmetrical
stripline strcture. But his solution should be able to help.

The situation Zhuyonffa mentioend is a much more complicated question
than the simple assumption as Steve made.
It is no more a qusi-TEM system, but it is still not too difficult to
understand from Electromagnetic field perspective.
All frequency range current can be flow back from the intact ground
plane, but only part of the frequency range current can travel the
power plane with split. In other words, some frequency current still
can travel through the splited power layer planes due to the
high-order EM field effect, whcih could be somewhat equivalent as
capacitance among the disconnected small planes on power layer.

With full-wave field solver, say HFSS or CST, you can clearly perceive
what is going on in your sestem.

Kinger

Kinger Consultant Adcanced
www.kingercai.com


On Nov 14, 2007 1:12 PM, Jack Olson <pcbjack@xxxxxxxxx> wrote:
> Yes, I can understand that quite easily.
> What is more difficult for me is to visualize it looking from the other way.
> Suppose a signal has a nice return path in close proximity, and they form a
> happy relationship before anything else happens. Then the signal path
> happens to pass near a metal bracket. Will some of the energy leave the
> "good" relationship to glom on to the bracket? So much so that if the
> bracket happens to be bolted to the surface of the board the same distance
> away as the return path, the energy will divide evenly?
> I honestly never thought that would happen. I imagined that some of the
> stray energy flux lines might be attracted to the new conductor, but not
> significant like 50/50. That's just scary!
>
> I assumed (in my shallow mental model) that the "good" return path would
> satisfy the signal path's deepest desires, and never the two would part.
>
> thanks for the enlightenment!
> Jack
>
>
> .
>
> On 11/14/07, steve weir <weirsi@xxxxxxxxxx> wrote:
> >
> > Jack, propagating fields are remarkably brain dead.  They just keep
> > expanding until they hit metal.  When they do, they penetrate a little,
> > but mostly they reflect.  As the field propagates it doesn't know that
> > there is a break ahead.  The wavefront reacts to the break when it hits
> > it.  Since the break represents a big change in the relative impedance,
> > the energy redistributes, exciting the slot, and draining power from the
> > forward propagating signal.
> >
> > Steve.
> > Jack Olson wrote:
> > > I can't resist asking a "newbie" question about your statement.
> > >
> > > Why would half of the energy couple to the broken-up plane,
> > > when it could couple to a beautiful solid continous conductive
> > > surface just to the other side?
> > > Won't a field form in the "space" of least impedance?
> > > Is it because the frequency is too high?
> > >
> > > Don't answer if its too lame-brained to bother with, ok?
> > > (One of these days I'm gonna "read up" on this stuff... sorry)
> > >
> > > Jack (aka "the new guy")
> > >
> > >
> > > On 11/14/07, *steve weir* <weirsi@xxxxxxxxxx
> > > <mailto:weirsi@xxxxxxxxxx>> wrote:
> > >
> > >     Zhuyongfa, yes layer 4 acts as a reflection plane to layer 3
> > signals.
> > >     Your current stack-up is a nearly symmetric stripline.  About half
> > >     the
> > >     energy will be bound between traces on layer 3 and each of the plane
> > >     layers 2, and 4.  Where single ended or in-phase differential
> > signals
> > >     cross moats on layer 4, energy will go into exciting the
> > >     slots.  Signal
> > >     rise-time, crosstalk, and EMI will all be affected.  To know the
> > exact
> > >     extent, you would need to simulate.
> > >
> > >     You can fix this by adjusting the stack-up to reduce coupling from
> > >     layer
> > >     3 signals to layer 4 etch by moving layer 3 closer to layer 2, and
> > >     further from layer 4.  Do the same thing with layer 8 wrt layers 9
> > and
> > >     7.  If you use 4 / 11 in place of your current 7 / 8 you will remove
> > >     almost all of the coupling from layer 3 to layer 4.
> > >
> > >     Good luck.
> > >
> > >     Steve.
> > >
> > >     z46147 wrote:
> > >     > Content-type: text/plain; charset=gb2312
> > >     > Content-transfer-encoding: 7BIT
> > >     > Hi all,
> > >     >
> > >     > A ten layers high speed PCB, the second layer is GND, the third
> > >     layer is signal, the fourth is Power layer.
> > >     >
> > >     > GND plane is a full one, never been splited. Several types of
> > >     voltage are on the power layer, so the power layer is isolated by
> > >     so many moats.
> > >     >
> > >     > Thickness between the second and third layer is 7 mil, while 8
> > >     mil between the third and fourth layer.
> > >     >
> > >     > Some high speed signals traces are routed on the third layer,
> > >     such as PCI Express and SAS/SATA signals.
> > >     >
> > >     > If the high speed signal traces go across isolation moat of the
> > >     fourth power layer, can it be treated as crossing split reference
> > >     plane and give rise to signal integrity problem?
> > >     >
> > >     > If it will give rise to signal integrity problem, can we use
> > >     stiching capacitors across isolation moats of the power layer to
> > >     deal with this issue, while changing the
> > >     > isolation moats?
> > >     >
> > >     > Any thought on this issue would be appreciated.
> > >     >
> > >     > Best regards.
> > >     >
> > >     >
> > >     > Zhuyongfa
> > >     > HUAWEI TECHNOLOGIES CO.,LTD.
> > >     >
> > >     >
> > >     > Address: Huawei Industrial Base
> > >     > Bantian Longgang
> > >     > Shenzhen 518129, P.R.China
> > >     > Tel:+86-755-89653025
> > >     > Fax: +86-755-89650731
> > >     > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx>
> > >     > www.huawei.com <http://www.huawei.com>
> > >     >
> >
> >
>
>
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