[SI-LIST] Re: High speed signals go across isolation moat

Content-type: text/plain; charset=ISO-8859-1
Content-transfer-encoding: 7BIT
Don,

Most of the gap width in the power plane is 30 mil, it seems that we had better 
reduce it to 20 mil.

Thanks and regards.


Zhuyongfa
HUAWEI TECHNOLOGIES CO.,LTD.  


Address: Huawei Industrial Base
Bantian Longgang
Shenzhen 518129, P.R.China
Tel:+86-755-89653025 
Fax: +86-755-89650731
E-mail: zhuyongfa@xxxxxxxxxx
www.huawei.com
-------------------------------------------------------------------------------------------------------------------------------------
This e-mail and its attachments contain confidential information from HUAWEI, 
which 
is intended only for the person or entity whose address is listed above. Any 
use of the 
information contained herein in any way (including, but not limited to, total 
or partial 
disclosure, reproduction, or dissemination) by persons other than the intended 
recipient(s) is prohibited. If you receive this e-mail in error, please notify 
the sender by 
phone or email immediately and delete it!

  ----- Original Message ----- 
  From: Don Nelson 
  To: zhuyongfa@xxxxxxxxxx 
  Cc: si-list@xxxxxxxxxxxxx ; duyumin@xxxxxxxxxx ; xiaoji@xxxxxxxxxx 
  Sent: Wednesday, November 14, 2007 10:28 PM
  Subject: [SI-LIST] Re: High speed signals go across isolation moat


  Hi Zhuyongfa,

    This is a question I've always wondered too: with two reference planes -- 
one solid and one split -- is there a good way to predict if the impedance 
discontinuity caused by a gap is enough to cause a signal integrity issue big 
enough to worry about.  I'm hoping someone else will weigh in on that point, 
particularly since your stackup suggests that most of the energy will be 
between the signal and the GND plane, it being closer.  Another factor working 
in your favor is that PCIe signals are differential, which I believe are more 
tolerant to reference plane gaps, so long as the gaps are small

    Still, if there *IS* a problem here big enough to worry about, I do not 
think that capacitors stiching the gap will help with fast signals like PCIe; 
the mounted inductance of a cap would likely be too high to be worth the 
trouble.  One solution (again, if a solution is actually warrented!) would be 
to run a second GND plane on Layer 5, with a very thin core/prepreg (like 2-3 
mils).  This would give you two benefits: one, you would form a nice low 
inductance capacitor for your return currents to hop across the gap.  If the 
gap in the plane is small (on the order of 10 mils), then the impedance 
discontinuity would be small relative to even very fast edges and your signals 
will be happy.

    the second benefit to this second GND plane is that you would gain a healty 
dose of plane capacitance in your power distribution network that would reduce 
its impedance at frequencies above what run-of-the-mill decoupling capacitors 
can achieve.  This is a nice side benefit that your PCIe chips will appreciate 
and might make your time in the EMI chamber less painful.

    The big question is: is there a problem here worth the trouble of fixing in 
the first place, and I would like to learn more about that topic myself!

  hope this helps,  
  -don
  --
  Don Nelson
  Ericsson
  Pittsburgh, PA
  "There are 10 kinds of people in this world: those who can count in binary 
and those who can't."

   
  On Wednesday, November 14, 2007, at 05:05AM, "z46147" <zhuyongfa@xxxxxxxxxx> 
wrote:
  >Content-type: text/plain; charset=gb2312
  >Content-transfer-encoding: 7BIT
  >Hi all,
  >
  >A ten layers high speed PCB, the second layer is GND, the third layer is 
signal, the fourth is Power layer.
  >
  >GND plane is a full one, never been splited. Several types of voltage are on 
the power layer, so the power layer is isolated by so many moats. 
  >
  >Thickness between the second and third layer is 7 mil, while 8 mil between 
the third and fourth layer.
  >
  >Some high speed signals traces are routed on the third layer, such as PCI 
Express and SAS/SATA signals.
  >
  >If the high speed signal traces go across isolation moat of the fourth power 
layer, can it be treated as crossing split reference plane and give rise to 
signal integrity problem?
  >
  >If it will give rise to signal integrity problem, can we use stiching 
capacitors across isolation moats of the power layer to deal with this issue, 
while changing the
  >isolation moats?
  > 
  >Any thought on this issue would be appreciated.
  >
  >Best regards.
  >
  >
  >Zhuyongfa
  >HUAWEI TECHNOLOGIES CO.,LTD.  
  >
  >
  >Address: Huawei Industrial Base
  >Bantian Longgang
  >Shenzhen 518129, P.R.China
  >Tel:+86-755-89653025 
  >Fax: +86-755-89650731
  >E-mail: zhuyongfa@xxxxxxxxxx
  >www.huawei.com
  
>-------------------------------------------------------------------------------------------------------------------------------------
  >This e-mail and its attachments contain confidential information from 
HUAWEI, which 
  >is intended only for the person or entity whose address is listed above. Any 
use of the 
  >information contained herein in any way (including, but not limited to, 
total or partial 
  >disclosure, reproduction, or dissemination) by persons other than the 
intended 
  >recipient(s) is prohibited. If you receive this e-mail in error, please 
notify the sender by 
  >phone or email immediately and delete it!
  >
  >
  >
  >-- Binary/unsupported file stripped by Ecartis --
  >-- Type: image/jpeg
  >-- File: outlook_huawei_logo_en.jpg
  >
  >
  >------------------------------------------------------------------
  >To unsubscribe from si-list:
  >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
  >
  >or to administer your membership from a web page, go to:
  >http://www.freelists.org/webpage/si-list
  >
  >For help:
  >si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
  >
  >
  >List technical documents are available at:
  >                http://www.si-list.net
  >
  >List archives are viewable at:     
  > http://www.freelists.org/archives/si-list
  >or at our remote archives:
  > http://groups.yahoo.com/group/si-list/messages
  >Old (prior to June 6, 2001) list archives are viewable at:
  > http://www.qsl.net/wb6tpu
  >  
  >
  >
  >
  ------------------------------------------------------------------
  To unsubscribe from si-list:
  si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

  or to administer your membership from a web page, go to:
  http://www.freelists.org/webpage/si-list

  For help:
  si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


  List technical documents are available at:
                  http://www.si-list.net

  List archives are viewable at:     
  http://www.freelists.org/archives/si-list
  or at our remote archives:
  http://groups.yahoo.com/group/si-list/messages
  Old (prior to June 6, 2001) list archives are viewable at:
    http://www.qsl.net/wb6tpu
    



-- Binary/unsupported file stripped by Ecartis --
-- Type: image/jpeg
-- File: outlook_huawei_logo_en.jpg


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: