Content-type: text/plain; charset=iso-8859-1 Content-transfer-encoding: 7BIT Steve, It is a good suggestion, but you know we have never tried the stack-up before. We always use a solid GND plane just underneath the devices(it means layer 2 of any board must be GND plane). Maybe we can try it. Zhuyongfa HUAWEI TECHNOLOGIES CO.,LTD. Address: Huawei Industrial Base Bantian Longgang Shenzhen 518129, P.R.China Tel:+86-755-89653025 Fax: +86-755-89650731 E-mail: zhuyongfa@xxxxxxxxxx www.huawei.com ------------------------------------------------------------------------------------------------------------------------------------- This e-mail and its attachments contain confidential information from HUAWEI, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure, reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it! ----- Original Message ----- From: steve weir To: z46147 Cc: si-list@xxxxxxxxxxxxx ; duyumin@xxxxxxxxxx ; xiaoji@xxxxxxxxxx Sent: Thursday, November 15, 2007 2:53 PM Subject: Re: [SI-LIST] Re: High speed signals go across isolation moat Zhuyongfa, a shield is often a patch applied to fix another problem. In the case of the earlier stack-up the PDN patches are strongly excited by signals on all of the internal routing layers, save layer 6. Transitions to / from any of the layers 3, 5, or 8 to / from layer 6 will also excite the PDN patches and all that connects to them, including the components on the top of the board, and any signals that go in and out of the box. The proposed stack-up gets rid of those problems by eliminating the signal coupling to the PDN patches. All the internal routing layers: 3, 5, 6, and 8 reference GND alone and do not excite the PDNs. There is still some cavity excitation, but this is readily dealt with by common measures as in adequate stitch via density particularly near the board edges. As an analogy: If you want peace and quiet you can either put lots of insulation between your apartment and your neighbors. But any open window will still be a problem. If instead you live next to quiet neighbors you can enjoy both the quiet and an open window. Steve. z46147 wrote: > Steve, > According to your suggestion, layer 2 and layer 9 are PWR planes, I > think it is not good for EMI performance. > Defining one or more GND plane outer will have good shield effect. > Any thought would be appreciated. > Regards. > Zhuyongfa > HUAWEI TECHNOLOGIES CO.,LTD. huawei_logo > Address: Huawei Industrial Base > Bantian Longgang > Shenzhen 518129, P.R.China > Tel:+86-755-89653025 > Fax: +86-755-89650731 > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx> > www.huawei.com <http://www.huawei.com> > ------------------------------------------------------------------------------------------------------------------------------------- > This e-mail and its attachments contain confidential information from > HUAWEI, which > is intended only for the person or entity whose address is listed > above. Any use of the > information contained herein in any way (including, but not limited > to, total or partial > disclosure, reproduction, or dissemination) by persons other than the > intended > recipient(s) is prohibited. If you receive this e-mail in error, > please notify the sender by > phone or email immediately and delete it! > > ----- Original Message ----- > *From:* steve weir <mailto:weirsi@xxxxxxxxxx> > *To:* z46147 <mailto:zhuyongfa@xxxxxxxxxx> > *Cc:* si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx> ; > duyumin@xxxxxxxxxx <mailto:duyumin@xxxxxxxxxx> ; xiaoji@xxxxxxxxxx > <mailto:xiaoji@xxxxxxxxxx> > *Sent:* Thursday, November 15, 2007 12:24 PM > *Subject:* [SI-LIST] Re: High speed signals go across isolation moat > > Zhuyongfa well that makes the problem more complicated. So what we > know > about the stack-up: > > 1 Top > 2 GND > 7mils > 3 Signal > 8 mils > 4 Power mixed > 5 ? presume signal > 6 ? presume signal > 7 GND > 8 mils > 8 ? presume signal > 7 mils > 9 Power mixed > 10 Bottom > > I suggest that this would work better: > > 1 Top > 2 Power mixed > 11 > 3 Signal > 4 mils > 4 GND > 4 mils > 5 signal > > 10 mils > 6 signal > 4 mils > 7 GND > 4 mils > 8 signal > 11 mils > 9 Power mixed > 10 Bottom > > All signal layers tightly reference GND, can readily change routing > layers as needed and will perform well. The distance from GND to > any of > the power layers hasn't changed so your bypass for IC power > delivery is > unchanged. But now the signals will not excite the PDN, making the > board > much quieter for a given bypass strategy. > > Steve. > > z46147 wrote: > > Steve, > > Adjusting the stack-up is not a good choice. > > Cause layer 2 and layer 7 are solid GND planes, and layer 4 and > layer > > 9 are power planes. > > If we move layer 3 close to layer 2, then layer 9 will be close to > > layer 8 too. Then high speed signal traces on layer 8 will go > across > > isolation moats on layer 9. > > Thanks and regards. > > Zhuyongfa > > HUAWEI TECHNOLOGIES CO.,LTD. huawei_logo > > > > Address: Huawei Industrial Base > > Bantian Longgang > > Shenzhen 518129, P.R.China > > Tel:+86-755-89653025 > > Fax: +86-755-89650731 > > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx> > <mailto:zhuyongfa@xxxxxxxxxx> > > www.huawei.com <http://www.huawei.com> <http://www.huawei.com> > > > ------------------------------------------------------------------------------------------------------------------------------------- > > This e-mail and its attachments contain confidential information > from > > HUAWEI, which > > is intended only for the person or entity whose address is listed > > above. Any use of the > > information contained herein in any way (including, but not limited > > to, total or partial > > disclosure, reproduction, or dissemination) by persons other > than the > > intended > > recipient(s) is prohibited. If you receive this e-mail in error, > > please notify the sender by > > phone or email immediately and delete it! > > > > ----- Original Message ----- > > *From:* steve weir <mailto:weirsi@xxxxxxxxxx> > > *To:* zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx> > <mailto:zhuyongfa@xxxxxxxxxx> > > *Cc:* si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx> > <mailto:si-list@xxxxxxxxxxxxx> ; > > duyumin@xxxxxxxxxx <mailto:duyumin@xxxxxxxxxx> > <mailto:duyumin@xxxxxxxxxx> ; xiaoji@xxxxxxxxxx > <mailto:xiaoji@xxxxxxxxxx> > > <mailto:xiaoji@xxxxxxxxxx> > > *Sent:* Wednesday, November 14, 2007 6:31 PM > > *Subject:* Re: [SI-LIST] High speed signals go across isolation moat > > > > Zhuyongfa, yes layer 4 acts as a reflection plane to layer 3 > signals. > > Your current stack-up is a nearly symmetric stripline. About > half the > > energy will be bound between traces on layer 3 and each of the plane > > layers 2, and 4. Where single ended or in-phase differential signals > > cross moats on layer 4, energy will go into exciting the slots. > > Signal > > rise-time, crosstalk, and EMI will all be affected. To know the > exact > > extent, you would need to simulate. > > > > You can fix this by adjusting the stack-up to reduce coupling from > > layer > > 3 signals to layer 4 etch by moving layer 3 closer to layer 2, and > > further from layer 4. Do the same thing with layer 8 wrt layers > 9 and > > 7. If you use 4 / 11 in place of your current 7 / 8 you will remove > > almost all of the coupling from layer 3 to layer 4. > > > > Good luck. > > > > Steve. > > > > z46147 wrote: > > > Content-type: text/plain; charset=gb2312 > > > Content-transfer-encoding: 7BIT > > > Hi all, > > > > > > A ten layers high speed PCB, the second layer is GND, the third > > layer is signal, the fourth is Power layer. > > > > > > GND plane is a full one, never been splited. Several types of > > voltage are on the power layer, so the power layer is isolated by > > so many moats. > > > > > > Thickness between the second and third layer is 7 mil, while 8 > > mil between the third and fourth layer. > > > > > > Some high speed signals traces are routed on the third layer, > > such as PCI Express and SAS/SATA signals. > > > > > > If the high speed signal traces go across isolation moat of the > > fourth power layer, can it be treated as crossing split reference > > plane and give rise to signal integrity problem? > > > > > > If it will give rise to signal integrity problem, can we use > > stiching capacitors across isolation moats of the power layer to > > deal with this issue, while changing the > > > isolation moats? > > > > > > Any thought on this issue would be appreciated. > > > > > > Best regards. > > > > > > > > > Zhuyongfa > > > HUAWEI TECHNOLOGIES CO.,LTD. > > > > > > > > > Address: Huawei Industrial Base > > > Bantian Longgang > > > Shenzhen 518129, P.R.China > > > Tel:+86-755-89653025 > > > Fax: +86-755-89650731 > > > E-mail: zhuyongfa@xxxxxxxxxx <mailto:zhuyongfa@xxxxxxxxxx> > <mailto:zhuyongfa@xxxxxxxxxx> > > > www.huawei.com <http://www.huawei.com> <http://www.huawei.com> > > > > > > ------------------------------------------------------------------------------------------------------------------------------------- > > > This e-mail and its attachments contain confidential information > > from HUAWEI, which > > > is intended only for the person or entity whose address is > > listed above. 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