[SI-LIST] Re: Ground, the preferred reference plane

From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
Date: Wed, 11 Dec 2002 20:59:05 -0800

Ok, I'll take your word and take the SI out of this discussion. So if I
design a package using ground plane as a reference for the PECL circuit in
the package. Guess what, if someone use it as ECL, that plane will become
-ve voltage. It may then blow up as you so worry about. Damn if you do, damn
if you don't isn't it.

-----Original Message-----
From: Michael J. Degerstrom [mailto:degers@xxxxxxxxxxxxxxxxxxxx]
Sent: Wednesday, December 11, 2002 8:40 PM
To: chris.cheng@xxxxxxxxxxxx; 'si-list@xxxxxxxxxxxxx'
Subject: Re: [SI-LIST] Re: Ground, the preferred reference plane

Chris,

Once again - if you take the time to read my original post I said that for 
this thread people were using the word 'reference' to mean two very
different 
things:

a) In the context of one or more reference planes that set the
characteristic 
impedance for the signal. These planes will carry the local return current 
for the signal.

b) In the context of a selected voltage that dictates how circuits interact 
with one another.  For example, consider two ECL chips with external VBB
pins 
that are powered from the same VBB on-board supply.  Since these two chips 
have the same switch point voltage reference then they behave very well 
together.  There are cases, where for example, you may want to run these ECL

chips with a positive voltage in an PECL .   This is often times fine to do 
but if there were grounded metal cases and heat sinks these metal surfaces 
will then be at the positive supply.  I merely mentioned in passing that you

may not want a design with large areas of bare metal at a non-ground 
potential as the risk of DC shorts during testing, handling, etc., would be 
high.  Please don't read any more into this passing comment - it had no 
relevance to high speed SI issues.

Mike

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[SI-LIST] Re: Ground, the preferred reference plane

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