[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability
- From: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>
- To: "Dimiter Popoff" <dp@xxxxxxxxxxx>
- Date: Fri, 3 Mar 2006 11:45:07 -0500
Dimiter,
I believe the process is IBM 130 nm. With regards to the energy the spikes
are roughly 2 ns long and the clock frequency is 100 MHz.
Thanks,
/Mikhail
----- Original Message -----
From: "Dimiter Popoff" <dp@xxxxxxxxxxx>
To: <matusov@xxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Friday, March 03, 2006 10:42 AM
Subject: Re: [SI-LIST] Effects of overshoot/undershoot on long-term
reliability
> I guess it would depend not just on the peak voltage but on
> the energy in that peak (i.e. peak area).
> I don't know what technology the DSP is - overshoots
> like this should matter somewhere about 130 nm and below,
> if older, chances are you will face no problems (but
> we'll know for sure after several years :-).
> If 130 nm and below, it would really be an interesting
> experiment to have one board constantly on until it fails - after
> days, months or years ? Really interesting, if you make such an
> experiment please keep us posted.
>
> Dimiter
>
>
> ------------------------------------------------------
> Dimiter Popoff Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------
>
>
> > -------Original Message-------
> > From: Mikhail Matusov <matusov@xxxxxxxxxxxx>
> > Subject: [SI-LIST] Effects of overshoot/undershoot on long-term
reliability
> > Sent: Mar 03 '06 17:34
> >
> > Dear experts,
> >
> > I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation
board
> > schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board it is
> > directly connected to a 3.3V Micron SDRAM. Unfortunately, we had not
> > simulated this interface before going into the layout. When we did we
found
> > that there is a huge overshoot on SDRAM read reaching almost 5V at the
DSP
> > pins. Our SI subcontractor recommends adding series terminations at the
> > SDRAM pins. At this point it would mean major PCB redesign. I pulled an
> > EZ-KIT card and captured the read cycle to verify the simulation
results and
> > found that the board behaves exactly as in simulation, i.e. the DSP
chip is
> > constantly subjected to this huge overshoot. However, the board works
fine.
> > So, I was wondering how I could estimate the risk of leaving the design
as
> > is?
> >
> >
> > Thanks,
> > =======================
> > Mikhail Matusov
> > Hardware Design Engineer
> > Square Peg Communications
> > Tel.: +1 (613) 271-0044 ext.231
> > Fax: +1 (613) 271-3007
> > http://www.squarepeg.ca
> >
> >
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