[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability
- From: steve weir <weirsi@xxxxxxxxxx>
- To: matusov@xxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 03 Mar 2006 07:52:44 -0800
Mikhail, will you have a warranty or liability problem if these
things fail within a particular period of time? Will your company
suffer loss of market if these things have a short life? If the
answer is yes, then you are pretty much stuck doing the homework to
first get a real answer out of ADI about what their parts can take
compared to what you are banging them with.
Personally, I would eat the redesign and sleep well at night knowing
that the product wasn't a Challenger disaster waiting to happen.
You might be able to get out of Dutch in the short term by applying
cost with an Ohmega layer for the resistors.
Steve.
At 07:34 AM 3/3/2006, Mikhail Matusov wrote:
>Dear experts,
>
>I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation board
>schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board it is
>directly connected to a 3.3V Micron SDRAM. Unfortunately, we had not
>simulated this interface before going into the layout. When we did we found
>that there is a huge overshoot on SDRAM read reaching almost 5V at the DSP
>pins. Our SI subcontractor recommends adding series terminations at the
>SDRAM pins. At this point it would mean major PCB redesign. I pulled an
>EZ-KIT card and captured the read cycle to verify the simulation results and
>found that the board behaves exactly as in simulation, i.e. the DSP chip is
>constantly subjected to this huge overshoot. However, the board works fine.
>So, I was wondering how I could estimate the risk of leaving the design as
>is?
>
>
>Thanks,
>=======================
>Mikhail Matusov
>Hardware Design Engineer
>Square Peg Communications
>Tel.: +1 (613) 271-0044 ext.231
>Fax: +1 (613) 271-3007
>http://www.squarepeg.ca
>
>
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