[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability
- From: "Curt McNamara" <CurtM@xxxxxxxxxxx>
- To: <matusov@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 3 Mar 2006 14:00:13 -0600
I agree with all the previous comments about fixing this and/or finding
the exact overshoot spec. for the part in question.=20
But --- how careful were you with probing techniques when taking these
measurements? FET probes (or even better differential probes) are the
best since the ground is immediately adjacent to the signal. If you have
to use a standard probe then fashioning a custom short ground lead is
recommended. Doug Smith's _High Frequency Measurements_ is the best
reference here, Johnson/Graham _High Speed Digital Design_ also has good
advice. You can get a FET probe for ~$600 last time I checked. The probe
needs to be calibrated to the scope as well!
Curt
Curt McNamara. P.E.=20
Senior Electrical Engineer=20
Logic Product Development=20
411 Washington Ave. N Suite 101=20
Minneapolis, MN 55401=20
Tel 612-436-5178=20
Fax 612-672-0443=20
curtm@xxxxxxxxxxx=20
www.logicpd.com=20
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Mikhail Matusov
Sent: Friday, March 03, 2006 9:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Effects of overshoot/undershoot on long-term
reliability
Dear experts,
I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation
board schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board
it is directly connected to a 3.3V Micron SDRAM. Unfortunately, we had
not simulated this interface before going into the layout. When we did
we found that there is a huge overshoot on SDRAM read reaching almost 5V
at the DSP pins. Our SI subcontractor recommends adding series
terminations at the SDRAM pins. At this point it would mean major PCB
redesign. I pulled an EZ-KIT card and captured the read cycle to verify
the simulation results and found that the board behaves exactly as in
simulation, i.e. the DSP chip is constantly subjected to this huge
overshoot. However, the board works fine. So, I was wondering how I
could estimate the risk of leaving the design as is?
Thanks,
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: +1 (613) 271-0044 ext.231
Fax: +1 (613) 271-3007
http://www.squarepeg.ca
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