[SI-LIST] Effects of overshoot/undershoot on long-term reliability
- From: "Mikhail Matusov" <matusov@xxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 3 Mar 2006 10:34:13 -0500
Dear experts,
I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation board
schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board it is
directly connected to a 3.3V Micron SDRAM. Unfortunately, we had not
simulated this interface before going into the layout. When we did we found
that there is a huge overshoot on SDRAM read reaching almost 5V at the DSP
pins. Our SI subcontractor recommends adding series terminations at the
SDRAM pins. At this point it would mean major PCB redesign. I pulled an
EZ-KIT card and captured the read cycle to verify the simulation results and
found that the board behaves exactly as in simulation, i.e. the DSP chip is
constantly subjected to this huge overshoot. However, the board works fine.
So, I was wondering how I could estimate the risk of leaving the design as
is?
Thanks,
=======================
Mikhail Matusov
Hardware Design Engineer
Square Peg Communications
Tel.: +1 (613) 271-0044 ext.231
Fax: +1 (613) 271-3007
http://www.squarepeg.ca
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