[SI-LIST] Re: Dead Band in PLL
- From: steve weir <weirsp@xxxxxxxxxx>
- To: parthsv@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 19 Nov 2003 06:20:50 -0800
There are techniques to reduce the dead-band, some of which are the subject
of patents by Analog Devices. ADI's patents cover a particular combination
of PFD and XOR phase detector, such that the PFD pulls the loop into
frequency lock and the XOR multiplier maintains phase lock. The jitter
performance of the ADI solution can be much better than alternatives, the
most common of which is an intentional phase offset. Both techniques
suffer from jitter susceptibility to power supply noise.
There are also other techniques that I own that allow for 0 phase offset
and very low jitter. In the case of either ADI, or my methods, a license
is required.
If you are looking for public domain, you can find clues in titles by
either Gardner, or Best.
Regards,
Steve.
At 03:46 AM 11/19/2003 -0800, Parthasarathy Sampath wrote:
>Hi All,
> How does one reduce/avoid Dead Band in PFD. The
>usual one is to rely on small glitch generated by Two
>Flip-Flops (in case PFD is based on FF design). Is it
>the standard in the industry
> Also, if the PFD is different from FF's,say based on
>NOR gates, how does one reduce the dead band?
>
>Thanks in Advance,
>
>Regards,
>Partha!
>
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