[SI-LIST] Re: Dead Band in PLL
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 19 Nov 2003 11:48:36 -0800
If you can tolerate a slight ~10ps static offset, the classic non-dead zone
design extend both the up and down pulse to a non-zero pulse width at zero
phase error by slightly delaying the reset circuits of the PFD. A carefully
design PFD and VCO combo can optimize the natural operating point of VCO at
the desire frequency to be close to what the charge pump wants to stay when
both up and down pulse are on during zero phase error. Phase error around
10ps is not uncommon. This is usually acceptable to most large ASIC designs
since the clock tree balance tolerance is worst than that anyways.
-----Original Message-----
From: Parthasarathy Sampath [mailto:parthsv@xxxxxxxxx]
Sent: Wednesday, November 19, 2003 3:46 AM
To: si-list@xxxxxxxxxxxxx
Cc: analogcmos_vlsi@xxxxxxxxxxxxxxx
Subject: [SI-LIST] Dead Band in PLL
Hi All,
How does one reduce/avoid Dead Band in PFD. The
usual one is to rely on small glitch generated by Two
Flip-Flops (in case PFD is based on FF design). Is it
the standard in the industry
Also, if the PFD is different from FF's,say based on
NOR gates, how does one reduce the dead band?
Thanks in Advance,
Regards,
Partha!
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