Posts for si-list, 11-2003

Browse: Last Month: 10-2003 Main Archive Page Next Month: 12-2003

» [SI-LIST] Looking for SPICE Model -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Separating SSO contributed by board vs device -
» [SI-LIST] Re: Separating SSO contributed by board vs device -
» [SI-LIST] Re: VHDL-AMS -
» [SI-LIST] Re: Via model -
» [SI-LIST] Parallel plate mode -
» [SI-LIST] VHDL-AMS -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Parallel plate mode -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] six layers board -
» [SI-LIST] Re: Hspice Fieldsolver Question -
» [SI-LIST] Internal inductance model -
» [SI-LIST] Re: Hspice Fieldsolver Question -
» [SI-LIST] Re: Via model -
» [SI-LIST] Re: Via model -
» [SI-LIST] R: Re: clock divider -
» [SI-LIST] Re: clock divider -
» [SI-LIST] Re: clock divider -
» [SI-LIST] Via model -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: clock divider -
» [SI-LIST] Two PLL's sequentional connection -
» [SI-LIST] Re: clock divider -
» [SI-LIST] clock divider -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: Transmission Lines Information -
» [SI-LIST] Signal Conditioning Cable Assemblies -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] 6 layers PCB -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] TDR and line losses -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Split Vdd for DDR -
» [SI-LIST] MDIO HW/SW -
» [SI-LIST] Transmission Lines Information -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] second call for papers: ICCS 2004:Workshop on Simulation and Modeling of 3D Integrated Circuits -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: Questions on losses of transmission line -
» [SI-LIST] Re: Hspice Fieldsolver Question -
» [SI-LIST] Questions on losses of transmission line -
» [SI-LIST] Re: Hspice Fieldsolver Question -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: "dominant" losses -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: Split Vdd for DDR -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] "dominant" losses -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Separating SSO contributed by board vs device -
» [SI-LIST] Split Vdd for DDR -
» [SI-LIST] Re: HSPICE stimulus question -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] s2ibis2 Spice model file specification -
» [SI-LIST] Hspice Fieldsolver Question -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Hspice T-elements in AC sweep? -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: Wishing Everyone a Happy Thanksgiving -
» [SI-LIST] Re: Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Dielectric constant for FR4 at above 1Ghz frequency -
» [SI-LIST] Re: HSPICE stimulus question -
» [SI-LIST] HSPICE stimulus question -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] RMCEMC Dec meeting - Registration closes Dec 1st -
» [SI-LIST] ESD and connector testing -
» [SI-LIST] R: high speed PCB design -
» [SI-LIST] various system backplanes -
» [SI-LIST] high speed PCB design -
» [SI-LIST] Re: Current Sharing of Parallel -48V Power supplies -
» [SI-LIST] Current Sharing of Parallel -48V Power supplies -
» [SI-LIST] Reflection problem due to multi drop of shard bus -
» [SI-LIST] Re: EMI/EMC Conference in Chennai, India -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] EMI/EMC Conference in Chennai, India -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] IBIS ICM 1.0.0 Parser On-line! -
» [SI-LIST] Re: Fastcap main manual -
» [SI-LIST] Re: PCB Design Guidelines -
» [SI-LIST] Re: Fastcap main manual -
» [SI-LIST] Re: PCB Design Guidelines -
» [SI-LIST] Fastcap main manual -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] Re: TDR and line losses -
» [SI-LIST] TDR and line losses -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: IBIS models - not all created equal? -
» [SI-LIST] Re: IBIS models - not all created equal? -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] IBIS models - not all created equal? -
» [SI-LIST] EMI/EMC Conference in Chennai, India -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: charge Pump Current in PFD -
» [SI-LIST] Re: what is the major difference b/w Ibis 3.2 & 3.3 -
» [SI-LIST] charge Pump Current in PFD -
» [SI-LIST] FW: [HireTopTalent-Ottawa] Job Opportunity -
» [SI-LIST] Algorithm to interpolate ramp data in IBIS -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: s2ibis2 utility -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Re: Noise in PCB vias -
» [SI-LIST] Re: SDRAM Timing -
» [SI-LIST] s2ibis2 utility -
» [SI-LIST] Noise in PCB vias -
» [SI-LIST] Re: what is the major difference b/w Ibis 3.2 & 3.3 -
» [SI-LIST] Re: what is the highest IBIS model being supported by hyperlynx -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] what is the major difference b/w Ibis 3.2 & 3.3 -
» [SI-LIST] what is the highest IBIS model being supported by hyperlynx -
» [SI-LIST] what is the highest IBIS model being supported by hyperlynx -
» [SI-LIST] Re: Compensation scheme in two-stage opamp -
» [SI-LIST] Re: Compensation scheme in two-stage opamp -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Re: PC board materials -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Compensation scheme in two-stage opamp -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Re: PC board materials -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Signal Integrity / Package Modeling Job Opening -
» [SI-LIST] Re: WG: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Re: Dead Band in PLL -
» [SI-LIST] Dead Band in PLL -
» [SI-LIST] WG: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: PC board materials -
» [SI-LIST] Re: PC board materials -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] PC board materials -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: PSPICE AC Sweep -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: Question -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Thomas Krzesaj/genius is out of the office. -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Dear Doug Brooks -
» [SI-LIST] Re: Question -
» [SI-LIST] Question -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: Doug Brooks's Question -
» (no subject) -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: IBIS Model error -
» [SI-LIST] Re: PSPICE AC Sweep -
» [SI-LIST] IBIS Model error -
» [SI-LIST] Re: Kelvin Functions -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Re: Cmos I/O & GTL I/O -
» [SI-LIST] Fwd: RE: Re: Doug Brooks's Question -
» [SI-LIST] Fwd: RE: Doug Brooks's Question -
» [SI-LIST] Re: Doug Brooks's Question -
» [SI-LIST] Doug Brooks's Question -
» [SI-LIST] Cmos I/O & GTL I/O -
» [SI-LIST] Re: EM simulation -
» [SI-LIST] Re: Doug Brooks's Question -
» [SI-LIST] Re: Doug Brooks's Question -
» [SI-LIST] Re: Doug Brooks's Question -
» [SI-LIST] EM simulation -
» [SI-LIST] Doug Brooks's Question -
» [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] PSPICE AC Sweep -
» [SI-LIST] Kelvin Functions -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: HSPICE Problem: **warning** Inconsistent data between The computed Vmax and the given value : Rising Waveform -
» [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: HSPICE Problem: **warning** Inconsistent data between The computed Vmax and the given value : Rising Waveform -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] stupid VNA / TDR / TDT Measurement / Setup question -
» [SI-LIST] Re: HSPICE Problem: **warning** Inconsistent data between Thecomputed Vmax and the given value : Rising Waveform -
» [SI-LIST] =?big5?q?=A6^=ABH=A1G?= RE: HSPICE Problem: **warning** Inconsistent data between The computedVmax and the given value : Rising Waveform -
» [SI-LIST] How to solve HSPICE Warning: underflow -
» [SI-LIST] HSPICE Problem: **warning** Inconsistent data between The computed Vmaxand the given value : Rising Waveform -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: Hspice subckt call -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Hspice Network Analysis now correlates -
» [SI-LIST] Hspice subckt call -
» [SI-LIST] Re: Hspice Network Analysis -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] Re: Antw: Scattering parameters for "typical" vias -
» [SI-LIST] Re: HSPICE Problem: **warning** element name <oldname> is truncated as <newname> -
» [SI-LIST] Re: Antw: Scattering parameters for "typical" vias -
» [SI-LIST] Re: Hypertransport(HT) to Ethernet Bridge solutions -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] IMD and substrate thickness -
» [SI-LIST] Re: Hypertransport(HT) to Ethernet Bridge solutions -
» [SI-LIST] Re: Hspice Network Analysis -
» [SI-LIST] Regarding postings to si-list -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Hspice Network Analysis -
» [SI-LIST] Re: HSPICE Problem: **warning** element name <oldname> is truncated as <newname> -
» [SI-LIST] Re: QDRII clock design -
» [SI-LIST] Re: IBIS series component example files -
» [SI-LIST] Hypertransport(HT) to Ethernet Bridge solutions -
» [SI-LIST] QDRII clock design -
» [SI-LIST] Antw: Scattering parameters for "typical" vias -
» [SI-LIST] For check -
» [SI-LIST] HSPICE Problem: **warning** element name <oldname> is truncated as <newname> -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] Proposed Launch (was TDR Recommendations) -
» [SI-LIST] Re: Transmission line match -
» [SI-LIST] Transmission line match -
» [SI-LIST] TDR Recommendations -
» [SI-LIST] Re: Resistance of Earth -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: SSTL2 / HSTL Input buffer -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: SSTL2 / HSTL Input buffer -
» [SI-LIST] Re: Capacitor Vendor -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] SSTL2 / HSTL Input buffer -
» [SI-LIST] Hspice Network Analysis -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: Scattering parameters for "typical" vias -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Scattering parameters for "typical" vias -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Right The First Time (the book) -
» [SI-LIST] Capacitor Vendor -
» [SI-LIST] Re: PLEASE QUIT THIS STUFF and GET TECHNICAL AGAIN! -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: TDR Recommendations -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] FW: Samtec Connector Wizard Webinar - Connector Models -
» [SI-LIST] Re: [OT] Offshore engineering -
» [SI-LIST] SDRAM Timing -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] TDR Recommendations -
» [SI-LIST] =?big5?q?=A6^=ABH=A1G?= Where can I get DDR2 EBD ordesign file? -
» [SI-LIST] Re: Where can I get DDR2 EBD or design file? -
» [SI-LIST] Re: Where can I get DDR2 EBD or design file? -
» [SI-LIST] Where can I get DDR2 EBD or design file? -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro.... -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: Regarding all the 'book price' traffic -
» [SI-LIST] Re: Resistance of Earth -
» [SI-LIST] Re: How do you unsubscribe to this list? -
» [SI-LIST] Re: How do you unsubscribe to this list? -
» [SI-LIST] Re: Job Opening- Lead SI engineer -
» [SI-LIST] Job Opening- Lead SI engineer -
» [SI-LIST] Re: Resistance of Earth -
» [SI-LIST] [OT] Offshore engineering -
» [SI-LIST] Re: SI Intro for your review (If you need support o n High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support o n High Speed Design and Signal Integrity) -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] Re: inner Xtalk of a differential pair -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SI Intro for your review (If you need support on HighSpeed Design and Signal Integrity) -
» [SI-LIST] Re: Curve Tracing IO pins at high state -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] How do you unsubscribe to this list? -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: question about hspice -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Re: SPICE model of 74VHC04 and SN74LV123A -
» [SI-LIST] SPICE model of 74VHC04 and SN74LV123A -
» [SI-LIST] Resistance of Earth -
» [SI-LIST] Curve Tracing IO pins at high state -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] RMCEMC December Social Event and Technical Presentation -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] pci Ton and Toff test load -
» [SI-LIST] the effect of power noise on IC -
» [SI-LIST] Re: SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] SI Intro for your review (If you need support on High Speed Design and Signal Integrity) -
» [SI-LIST] Heisenberg in the Frequency Domain -
» [SI-LIST] Re: question about hspice -
» [SI-LIST] Re: inner Xtalk of a differential pair -
» [SI-LIST] inner Xtalk of a differential pair -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Reminder: SCV EMC Society Mtg; Prof. Todd Hubing, Nov. 11 in Santa Clara -
» [SI-LIST] Reminder: SCV EMC Society Mtg; Prof. Todd Hubing, Nov. 11 in Santa Clara -
» [SI-LIST] Re: question about hspice -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] req. for information ralted to Nx64 service -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] Question Regarding Simulations -
» [SI-LIST] Re: Embedded uStrip - double check me -
» [SI-LIST] Re: Resistor construction for high frequency operation -
» [SI-LIST] Resistor construction for high frequency operation -
» [SI-LIST] unsubscribe -
» [SI-LIST] question about hspice -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] Re: SI tools -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] Re: SI tools -
» [SI-LIST] Re: SI tools -
» [SI-LIST] si engineer wanted -
» [SI-LIST] Re: Lee Ritchey's book -
» [SI-LIST] Re: Lee Ritchey's book -
» [SI-LIST] Re: relative magnetic permeability of tungsten,mol ybdenum... proving hard to find -
» [SI-LIST] Re: SI tools -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] Good morning -
» [SI-LIST] Re: Linear/Switching Power Supplies -
» [SI-LIST] Re: Digest Number 896 -
» [SI-LIST] Linear/Switching Power Supplies -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybde num... proving hard to find -
» [SI-LIST] About the concept -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] Re: SI tools -
» [SI-LIST] Re: 50Ohm Antenna -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] IBIS series component example files -
» [SI-LIST] Re: EMC -
» [SI-LIST] extra power copper on inner layers -
» [SI-LIST] Re: SI tools -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... provinghard to find -
» [SI-LIST] Re: Embedded uStrip - double check me -
» [SI-LIST] Re: relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] Re: PECL to CMOS conversion -
» [SI-LIST] SI tools -
» [SI-LIST] Re: Embedded uStrip - double check me -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] relative magnetic permeability of tungsten, molybdenum... proving hard to find -
» [SI-LIST] Re: Embedded uStrip - double check me -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: IBIS Models -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: PECL to CMOS conversion -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] IBIS Models -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] PECL to CMOS conversion -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: Lee Ritchey's book -
» [SI-LIST] Re: Question about implementing capacitors on IC -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] Re: Lee Ritchey's book -
» [SI-LIST] Re: FW: Embedded uStrip - double check me -
» [SI-LIST] FW: Embedded uStrip - double check me -
» [SI-LIST] Re: Question about implementing capacitors on IC -
» [SI-LIST] Question about implementing capacitors on IC -
» [SI-LIST] Re: Antw: Embedded uStrip - double check me -
» [SI-LIST] Re: EMC -
» [SI-LIST] Antw: Embedded uStrip - double check me -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: Recommendation for quick-turn board house -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] Recommendation for quick-turn board house -
» [SI-LIST] Embedded uStrip - double check me -
» [SI-LIST] Lee Ritchey's book -
» [SI-LIST] SI/CAD engineer available for employment -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: breakdown voltage (arching) equation -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: breakdown voltage (arching) equation -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: Best Method to measure Characteristic Impedance on a PCB Board -
» [SI-LIST] Re: impedance mismatch -
» [SI-LIST] EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Book from Bakoglu: Circuits, Interconnections, and Packaging for VLSI -
» [SI-LIST] impedance mismatch -
» [SI-LIST] Recall: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Re: EMC -
» [SI-LIST] Best Method to measure Characteristic Impedance on a PCB Board -
» [SI-LIST] EMC -
» [SI-LIST] SCV EMC Society Meeting Announcement: Prof. Tod Hubing, Nov. 11 in Santa Clara -
» [SI-LIST] Meeting Announcement: IPC-SVC on Nov. 11 in San Jose -
» [SI-LIST] Power homework, was: RE: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: breakdown voltage (arching) equation -
» [SI-LIST] Re: inductance of a reflowed solder bump -
» [SI-LIST] All Digital Phase Locked Loop -
» [SI-LIST] Re: Return Current of High-speed transmission line. -
» [SI-LIST] Re: breakdown voltage (arching) equation -
» [SI-LIST] inductance of a reflowed solder bump -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: About common-mode -
» [SI-LIST] Re: breakdown voltage (arching) equation -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» (no subject) -
» [SI-LIST] Return Current of High-speed transmission line. -
» [SI-LIST] breakdown voltage (arching) equation -
» [SI-LIST] Regarding all the 'book price' traffic -
» [SI-LIST] Re: About common-mode -
» [SI-LIST] Re: About common-mode -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Book Price -
» [SI-LIST] STOP MOANING -
» [SI-LIST] Re: FW: Re: Book Price -
» [SI-LIST] FW: Re: Book Price -
» [SI-LIST] Re: Book Price -
» [SI-LIST] Re: Books/references on power/grounddistribution -
» [SI-LIST] Book Price -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] About common-mode -
» [SI-LIST] Re: Books/references on power/grounddistribution -
» [SI-LIST] Re: Inappropriate remarks and personal attacks -
» [SI-LIST] Inappropriate remarks and personal attacks -
» [SI-LIST] Re: Books/references on power/grounddistribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/grounddistribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Spice simulators help -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: Books/references on power/ground distribution -