[SI-LIST] Re: Dead Band in PLL
- From: "Guo Yawei" <ywguo527@xxxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 20 Nov 2003 10:06:43 +0800
Hello, Chris,
About the said ~10ps static offset.
I think it is due to the unbalance up and down current in the charge pump.
Is my understanding right? If so, the static phase error depends on the
mismatch of the up and down current in the charge pump. Of course it is
very difficult to make the up and down current equal in practice. 10
percent current mismatch is not uncommon. So the up and down pulse
generated by PFD must have about 10 percent mismatch to compensate the
mismatch current in the charge pump. If the up and down pulse generated by
PFD have about 400ps (That is already very small. Do you think so), The
static phase error will be about 40ps.
Of course, ~40ps is still better that what clock tree can get in most large
ASIC.
Best Regards,
Yawei Guo
>From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
>Reply-To: chris.cheng@xxxxxxxxxxxx
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Dead Band in PLL
>Date: Wed, 19 Nov 2003 11:48:36 -0800
>
>If you can tolerate a slight ~10ps static offset, the classic non-dead
zone
>design extend both the up and down pulse to a non-zero pulse width at zero
>phase error by slightly delaying the reset circuits of the PFD. A
carefully
>design PFD and VCO combo can optimize the natural operating point of VCO
at
>the desire frequency to be close to what the charge pump wants to stay
when
>both up and down pulse are on during zero phase error. Phase error around
>10ps is not uncommon. This is usually acceptable to most large ASIC
designs
>since the clock tree balance tolerance is worst than that anyways.
>
>-----Original Message-----
>From: Parthasarathy Sampath [mailto:parthsv@xxxxxxxxx]
>Sent: Wednesday, November 19, 2003 3:46 AM
>To: si-list@xxxxxxxxxxxxx
>Cc: analogcmos_vlsi@xxxxxxxxxxxxxxx
>Subject: [SI-LIST] Dead Band in PLL
>
>
>Hi All,
> How does one reduce/avoid Dead Band in PFD. The
>usual one is to rely on small glitch generated by Two
>Flip-Flops (in case PFD is based on FF design). Is it
>the standard in the industry
> Also, if the PFD is different from FF's,say based on
>NOR gates, how does one reduce the dead band?
>
>Thanks in Advance,
>
>Regards,
>Partha!
>
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