[SI-LIST] Re: Dead Band in PLL
- From: "Guo Yawei" <ywguo527@xxxxxxxxxxx>
- To: chris.cheng@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 22 Nov 2003 01:16:45 +0800
Chris,
Of course I admit there are many applications such as downstream PLL on
microprocessor, clock recovery circuit used in serdes, SONET, infiniband,
PCI-express, etc. PFD is constructed using dynamic FF's, and the overlapped
pulse is very small in those high speed application.
Maybe I didn't show my opinion clearly enough. My main point is that the
static phase error is zero if mismatch and offset are negligible
(Monolithic Phase-Locked Loops and Clock Recovery Circuits, theory and
design, by Bezhad Razavi, IEEE Press, 1996, page 29). So for charge pump
PLL, where the VCO control voltage settles doesn't matter the phase error
theoretically.
Furthermore, I don't understand the term zero charge phase point that you
use. Could you explain it for me?
Maybe the example of 400ps pulse is not good. I respect your experience in
PLL design. However, I think it is not harmful when designing frequency
synthesizer with low frequency reference clock. Do you agree with me?
Best regards,
Yawei Guo
>From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
>Reply-To: chris.cheng@xxxxxxxxxxxx
>To: "'Guo Yawei'" <ywguo527@xxxxxxxxxxx>,Chris Cheng
<chris.cheng@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Dead Band in PLL
>Date: Thu, 20 Nov 2003 12:47:20 -0800
>
>I really don't know what to say, the PLL I worked on even in early 90's
have
>pulses less than 400ps. And while your claim of xtals from several to
dozen
>MHz may describe the very first stage of a clock distribution tree in a
>system, there are many more PLLs down stream locking to a much much higher
>speed reference clock. Just ask any designer working on DDR II, GDDR3 or
>zero delay fan out buffers for clock distribution.
>I also claim it is easy to predict where the zero charge phase point is
for
>a charge pump given a known VCO operating point. We can simulate and
measure
>it all the time.
>May be techniques to analyze PLL performance and designing phase detector
>pulses smaller than 400ps are core competencies of some of the companies I
>work for/with but rest assure they are here and well understood.
>Unfortunately, you will probably have to work for those companies to learn
>it. Good luck in finding one in your country. It is indeed fun to work on
>PLLs.
>
>-----Original Message-----
>From: Guo Yawei [mailto:ywguo527@xxxxxxxxxxx]
>Sent: Wednesday, November 19, 2003 9:00 PM
>To: chris.cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Dead Band in PLL
>
>
>Chris,
>
>I don't agree with you on the phase offset. Theoretially it is right that
>the phase offset is due to the difference between the VCO control voltage
>at the desire frequency and the net voltage where the charge pump will
>settle at when both up and down pulse are turn on. But please note that we
>are talking about charge PLL when we say up and down current in charge
>pump. Idealy, charge pump PLL has zero phase offset. So one of its
>important applicaton is deskew on PC board or on chip. However, due to
>mismatch current in charge pump, there must be very small phase error in
>practice.
>
>If you ask why charge pump PLL has zero phase error idealy, just because
>PFD+charge pump acts as an integrator, which means infinite DC gain. Any
>difference between the VCO control volatge at the desired frequency and
the
>net voltage where the charge pump settles is divided by infinite DC gain.
>Thus the phase error is zero idealy.
>
>Furthermore, we cannot determine where the charge pump settles because the
>up and current are sourced from and sinked in current source, which has
>very high impedance.
>
>For may PLLs used as frequency synthesizer, 400ps pulse is not very high
>because the refernece frequency is usually several to dozens MHz. Crystals
>with resonant frequency higher than 100MHz is more expensive.
>
>400ps is not uncommon because it is safe to avoid deadband in charge pump
>PLL.
>
>Very glad to discuss PLL with you.
>
>Best regards,
>Yawei Guo
>
>
> >From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
> >Reply-To: chris.cheng@xxxxxxxxxxxx
> >To: "'Guo Yawei'" <ywguo527@xxxxxxxxxxx>,Chris Cheng
><chris.cheng@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: Dead Band in PLL
> >Date: Wed, 19 Nov 2003 18:27:52 -0800
> >
> >Not exactly. You can have current mis-match in the up and down charge
>pump.
> >But the phase offset is due to the difference between the VCO control
> >voltage at the desire frequency and the net voltage the charge pump will
> >settle at when both up and down pulse are turn on. That delta will
result
>in
> >excess charge transfer in or out of the charge pump. However, if you
> >consider the short duration of the pulse compare with the cycle time, it
>is
> >only a fraction of the peak delta current (averaged over one cycle).
> >400ps sounds very high. Many PLL's have cycle time less than that
>(although
> >they may not compare phase every cycle).
> >
> >-----Original Message-----
> >From: Guo Yawei [mailto:ywguo527@xxxxxxxxxxx]
> >Sent: Wednesday, November 19, 2003 6:07 PM
> >To: chris.cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >Subject: Re: [SI-LIST] Re: Dead Band in PLL
> >
> >
> >Hello, Chris,
> >
> >About the said ~10ps static offset.
> >
> >I think it is due to the unbalance up and down current in the charge
pump.
> >Is my understanding right? If so, the static phase error depends on the
> >mismatch of the up and down current in the charge pump. Of course it is
> >very difficult to make the up and down current equal in practice. 10
> >percent current mismatch is not uncommon. So the up and down pulse
> >generated by PFD must have about 10 percent mismatch to compensate the
> >mismatch current in the charge pump. If the up and down pulse generated
by
> >PFD have about 400ps (That is already very small. Do you think so), The
> >static phase error will be about 40ps.
> >
> >Of course, ~40ps is still better that what clock tree can get in most
>large
> >ASIC.
> >
> >
> >Best Regards,
> >Yawei Guo
> >
> >
> >
> > >From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
> > >Reply-To: chris.cheng@xxxxxxxxxxxx
> > >To: si-list@xxxxxxxxxxxxx
> > >Subject: [SI-LIST] Re: Dead Band in PLL
> > >Date: Wed, 19 Nov 2003 11:48:36 -0800
> > >
> > >If you can tolerate a slight ~10ps static offset, the classic non-dead
> >zone
> > >design extend both the up and down pulse to a non-zero pulse width at
>zero
> > >phase error by slightly delaying the reset circuits of the PFD. A
> >carefully
> > >design PFD and VCO combo can optimize the natural operating point of
VCO
> >at
> > >the desire frequency to be close to what the charge pump wants to stay
> >when
> > >both up and down pulse are on during zero phase error. Phase error
>around
> > >10ps is not uncommon. This is usually acceptable to most large ASIC
> >designs
> > >since the clock tree balance tolerance is worst than that anyways.
> > >
> > >-----Original Message-----
> > >From: Parthasarathy Sampath [mailto:parthsv@xxxxxxxxx]
> > >Sent: Wednesday, November 19, 2003 3:46 AM
> > >To: si-list@xxxxxxxxxxxxx
> > >Cc: analogcmos_vlsi@xxxxxxxxxxxxxxx
> > >Subject: [SI-LIST] Dead Band in PLL
> > >
> > >
> > >Hi All,
> > > How does one reduce/avoid Dead Band in PFD. The
> > >usual one is to rely on small glitch generated by Two
> > >Flip-Flops (in case PFD is based on FF design). Is it
> > >the standard in the industry
> > > Also, if the PFD is different from FF's,say based on
> > >NOR gates, how does one reduce the dead band?
> > >
> > >Thanks in Advance,
> > >
> > >Regards,
> > >Partha!
> > >
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