[SI-LIST] Re: DDR Termination
- From: John Zasio <zasio@xxxxxxxxxxxxxxxxxxx>
- To: SSantangelo@xxxxxxxxxxxx
- Date: Fri, 25 Mar 2005 09:24:22 -0800
Hi Steve,
The main difference in my products between series and parallel
termination of DDR-1 DIMMS is
power dissipation. I have an ASIC that has six separate DDR-1 interfaces
running with series
terminated drivers and one DIMM per interface. There is a two Watt
difference per interface or
12 Watts per ASIC to use the parallel approach. The performance limit is
the round trip delay on
the DQS lines. The DIMM series termination consists of a 22 Ohm resistor
in series with the
output drive impedance of the memory chip. At the end of a read
operation the memory chip
DQS driver goes into the high impedance state one half clock cycle after
transmitting the last
clock edge to the controller. The reflection must get back to the memory
chip before it goes into
the high impedance state to be properly terminated.
Because of six separate memory interfaces some of the DIMMS have a total
PCB wire length
of six inches. I run the interfaces at a 150 MHz clock rate (300 Mbps
data rate).
John Zasio
Santangelo, Steven wrote:
>Hi,
>
>I'm looking at a DDR interface which consists of a controller and a =
>single SODIMM module. In the past we've successfully simulated, built =
>and tested this interface using only series terminations but have always =
>run it fairly slow, 100MHz or 133MHz. As we crank up the clock on =
>future designs I'm starting to wonder if we should switch to the more =
>standard series+parallel termination scheme. Aside from the increased =
>over and undershoot and any resulting EMI issues, I don't see a big =
>difference between the 2 approaches. If anything, the series only =
>approach appears to give me better noise margin due to the increased =
>swing. Should I be concerned about using the series termination only =
>approach when running at higher speeds, say 166MHz or 200MHz? What =
>areas should I be concerned about?
>
>Thanks
>
>Steve
> =20
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