[SI-LIST] Re: DDR Termination

Steven

The answer is: "Yes, you should be concerned."

The primary reason for the parallel termination to Vdd/2 is to center 
the switching around Vref.  At low speeds this is not critical. But at 
high speed, intersymbol interference (ISI) and pattern run lengths of 
all zeros and all ones will eat your timing margin alive.

There are two reasons for series termination. The first reason is to 
provide a better impedance match for the drivers.  The second reason to 
to provide resistive losses to de-Q resonances in the channel.  DDR even 
with series and parallel termination is not a well damped system.  At 
higher frequencies the channel resonances will kill you.


best regards,

scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Santangelo, Steven wrote:

>Hi,
>
>I'm looking at a DDR interface which consists of a controller and a =
>single SODIMM module.  In the past we've successfully simulated, built =
>and tested this interface using only series terminations but have always =
>run it fairly slow, 100MHz or 133MHz.   As we crank up the clock on =
>future designs I'm starting to wonder if we should switch to the more =
>standard series+parallel termination scheme.  Aside from the increased =
>over and undershoot and any resulting EMI issues, I don't see a big =
>difference between the 2 approaches.  If anything, the series only =
>approach appears to give me better noise margin due to the increased =
>swing.  Should I be concerned about using the series termination only =
>approach when running at higher speeds, say 166MHz or 200MHz?  What =
>areas should I be concerned about?
>
>Thanks
>
>Steve
> =20
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