[SI-LIST] Re: DDR Termination
- From: "Santangelo, Steven" <SSantangelo@xxxxxxxxxxxx>
- To: "Dan Bostan" <dbostan@xxxxxxxxx>, <scott@xxxxxxxxxxxxx>
- Date: Fri, 25 Mar 2005 14:31:42 -0500
Gentlemen,
Thanks for your responses. I guess what I'm missing here is not being =
able to see the timing margin issues. I've run many simulations of the =
series-only case in the past and have recently started running the =
series+parallel(S+P) cases. With an etch length of about 2.75" to the =
SODIMM and at speeds up to 200MHz (400Mbps), I don't really see any =
differences (timing wise) that would lead me to the S+P solution. At =
200MHz, am I still too slow (not me, the circuit) to have to worry about =
this or am I just looking at it wrong?=20
In response to one of the comments, I effectively do have series terms =
on both ends of the DQ and DQS lines since I have an on-board series =
term along with the 22ohm series term on the SODIMM itself.
Thanks again for your help.
Steve
-----Original Message-----
From: Dan Bostan [mailto:dbostan@xxxxxxxxx]
Sent: Friday, March 25, 2005 2:07 PM
To: scott@xxxxxxxxxxxxx; Santangelo, Steven
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR Termination
From my experience, the parrallel termination can be
eliminated, but only after reducing the length of
traces and extensive simulations to make sure SI and
timing are OK.
As Scott said, the timing margins are smaller without
the VTT parallel terminations.
/dan
--- Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
> Steven
>=20
> The answer is: "Yes, you should be concerned."
>=20
> The primary reason for the parallel termination to
> Vdd/2 is to center=20
> the switching around Vref. At low speeds this is
> not critical. But at=20
> high speed, intersymbol interference (ISI) and
> pattern run lengths of=20
> all zeros and all ones will eat your timing margin
> alive.
>=20
> There are two reasons for series termination. The
> first reason is to=20
> provide a better impedance match for the drivers.=20
> The second reason to=20
> to provide resistive losses to de-Q resonances in
> the channel. DDR even=20
> with series and parallel termination is not a well
> damped system. At=20
> higher frequencies the channel resonances will kill
> you.
>=20
>=20
> best regards,
>=20
> scott
>=20
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>=20
> http://www.teraspeed.com
>=20
> Teraspeed=AE is the registered service mark of
> Teraspeed Consulting Group LLC
>=20
>=20
>=20
> Santangelo, Steven wrote:
>=20
> >Hi,
> >
> >I'm looking at a DDR interface which consists of a
> controller and a =3D
> >single SODIMM module. In the past we've
> successfully simulated, built =3D
> >and tested this interface using only series
> terminations but have always =3D
> >run it fairly slow, 100MHz or 133MHz. As we crank
> up the clock on =3D
> >future designs I'm starting to wonder if we should
> switch to the more =3D
> >standard series+parallel termination scheme. Aside
> from the increased =3D
> >over and undershoot and any resulting EMI issues, I
> don't see a big =3D
> >difference between the 2 approaches. If anything,
> the series only =3D
> >approach appears to give me better noise margin due
> to the increased =3D
> >swing. Should I be concerned about using the
> series termination only =3D
> >approach when running at higher speeds, say 166MHz
> or 200MHz? What =3D
> >areas should I be concerned about?
> >
> >Thanks
> >
> >Steve
> > =3D20
>
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