[SI-LIST] Re: DDR Termination

Steve
Are you running long patterns with long run lengths of 1's and 0's 
followed by single pulses in the opposite direction?   Parallel 
termination to VDD/2 helps to center the transitions around Vref.

scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
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Santangelo, Steven wrote:

>Gentlemen,
>
>Thanks for your responses.  I guess what I'm missing here is not being able to 
>see the timing margin issues.  I've run many simulations of the series-only 
>case in the past and have recently started running the series+parallel(S+P) 
>cases.  With an etch length of about 2.75" to the SODIMM and at speeds up to 
>200MHz (400Mbps), I don't really see any differences (timing wise) that would 
>lead me to the S+P solution.  At 200MHz, am I still too slow (not me, the 
>circuit) to have to worry about this or am I just looking at it wrong? 
>
>In response to one of the comments, I effectively do have series terms on both 
>ends of the DQ and DQS lines since I have an on-board series term along with 
>the 22ohm series term on the SODIMM itself.
>
>Thanks again for your help.
>
>Steve
>
>
>
>
>-----Original Message-----
>From: Dan Bostan [mailto:dbostan@xxxxxxxxx]
>Sent: Friday, March 25, 2005 2:07 PM
>To: scott@xxxxxxxxxxxxx; Santangelo, Steven
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: DDR Termination
>
>
>>From my experience, the parrallel termination can be
>eliminated, but only after reducing the length of
>traces and extensive simulations to make sure SI and
>timing are OK.
>As Scott said, the timing margins are smaller without
>the VTT parallel terminations.
>/dan
>
>--- Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
>  
>
>>Steven
>>
>>The answer is: "Yes, you should be concerned."
>>
>>The primary reason for the parallel termination to
>>Vdd/2 is to center 
>>the switching around Vref.  At low speeds this is
>>not critical. But at 
>>high speed, intersymbol interference (ISI) and
>>pattern run lengths of 
>>all zeros and all ones will eat your timing margin
>>alive.
>>
>>There are two reasons for series termination. The
>>first reason is to 
>>provide a better impedance match for the drivers. 
>>The second reason to 
>>to provide resistive losses to de-Q resonances in
>>the channel.  DDR even 
>>with series and parallel termination is not a well
>>damped system.  At 
>>higher frequencies the channel resonances will kill
>>you.
>>
>>
>>best regards,
>>
>>scott
>>
>>Scott McMorrow
>>Teraspeed Consulting Group LLC
>>121 North River Drive
>>Narragansett, RI 02882
>>(401) 284-1827 Business
>>(401) 284-1840 Fax
>>
>>http://www.teraspeed.com
>>
>>Teraspeed® is the registered service mark of
>>Teraspeed Consulting Group LLC
>>
>>
>>
>>Santangelo, Steven wrote:
>>
>>    
>>
>>>Hi,
>>>
>>>I'm looking at a DDR interface which consists of a
>>>      
>>>
>>controller and a =
>>    
>>
>>>single SODIMM module.  In the past we've
>>>      
>>>
>>successfully simulated, built =
>>    
>>
>>>and tested this interface using only series
>>>      
>>>
>>terminations but have always =
>>    
>>
>>>run it fairly slow, 100MHz or 133MHz.   As we crank
>>>      
>>>
>>up the clock on =
>>    
>>
>>>future designs I'm starting to wonder if we should
>>>      
>>>
>>switch to the more =
>>    
>>
>>>standard series+parallel termination scheme.  Aside
>>>      
>>>
>>from the increased =
>>    
>>
>>>over and undershoot and any resulting EMI issues, I
>>>      
>>>
>>don't see a big =
>>    
>>
>>>difference between the 2 approaches.  If anything,
>>>      
>>>
>>the series only =
>>    
>>
>>>approach appears to give me better noise margin due
>>>      
>>>
>>to the increased =
>>    
>>
>>>swing.  Should I be concerned about using the
>>>      
>>>
>>series termination only =
>>    
>>
>>>approach when running at higher speeds, say 166MHz
>>>      
>>>
>>or 200MHz?  What =
>>    
>>
>>>areas should I be concerned about?
>>>
>>>Thanks
>>>
>>>Steve
>>>=20
>>>      
>>>
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