[SI-LIST] Re: DDR Termination

Steve,

To expound on what Scott and Steve have stated, a "series-only" termination
solution
looses the reference to Vterm. This can cause duty cycle distortion which
results in differing propagation delays for low-to-high and high-to-low
transitions. The delay effects will be data pattern dependent. Granted, if
timing
margins are large, this level of analysis is not warranted. But as we crank
up the DDR data rates, and the resulting timing margins reduce to 10's of
picoseconds, we will be thrust into concerning ourselves with the minutia of
every "component" that can cause delay differences from one signal to
another
within a specific timing group (which is the main concern for source
synchronous designs).

Some other delay skew factors to worry about in future "critical designs"
(occurring at DDR400 and above or where margins are insufficient) are :

- Using different layers to route signals. A data line routed on layer 3
versus a data line routed on layer 14 could cause 40-60 ps of delay
difference between the two signals due to via stub delay effects (depends on
board thickness, among other things).
- Likewise, using different routing layers (for a group) that have different
di-electric constants
(inherent with PCB design) will cause flight time delay differences because
the di-electric material is directly related to velocity factor.
- Crosstalk on the board. Crosstalk has the potential to speedup and slow
down signals in relation to other signals in a group that don't have
crosstalk. This is data pattern dependent so you could have a system working
flawlessly till a "killer data transfer" occurs. This is a "chase your tail"
kind of problem.
- Crosstalk in the package. Nothing we can do but it exists.
- Simultaneous switching noise. Nothing we can do but it has to be part of
the budget.
- Jitter in clock from controller.
- Jitter in PLL system (if applicable).
- Inter-symbol interference as discussed by others.
- Tolerance throughout the system (trace tolerance, passive component
tolerance, VREF tolerance as well as the normal process, voltage and
temperature tolerances).
- Input capacitance differences at the receiver
- Package skew differences from one signal to another (different delays
depending on location of the ball in the package).
- System noise (power supplies, VREF, random noise sources which translates
into jitter).
- Duty cycle mismatch due to differences in driver high-drive versus
low-drive (no drivers are perfect). In addition, signal integrity effects
can exacerbate the duty cycle problem, such as not providing a termination
to Vterm (VTT).
- Output driver skew (inherently, chip designers design in skew to reduce
SSO problems, among other sources of skew in the drivers).

Hope this helps...
Steve

Stephen P. Zinck
Interconnect Engineering
25 Bennett Lot Road
South Berwick, ME 03908
Phone - (207) 384-8280
Fax - (207) 384-5388
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com


----- Original Message ----- 
From: "Santangelo, Steven" <SSantangelo@xxxxxxxxxxxx>
To: "Dan Bostan" <dbostan@xxxxxxxxx>; <scott@xxxxxxxxxxxxx>
Cc: <si-list@xxxxxxxxxxxxx>
Sent: Friday, March 25, 2005 2:31 PM
Subject: [SI-LIST] Re: DDR Termination


> Gentlemen,
>
> Thanks for your responses.  I guess what I'm missing here is not being =
> able to see the timing margin issues.  I've run many simulations of the =
> series-only case in the past and have recently started running the =
> series+parallel(S+P) cases.  With an etch length of about 2.75" to the =
> SODIMM and at speeds up to 200MHz (400Mbps), I don't really see any =
> differences (timing wise) that would lead me to the S+P solution.  At =
> 200MHz, am I still too slow (not me, the circuit) to have to worry about =
> this or am I just looking at it wrong?=20
>
> In response to one of the comments, I effectively do have series terms =
> on both ends of the DQ and DQS lines since I have an on-board series =
> term along with the 22ohm series term on the SODIMM itself.
>
> Thanks again for your help.
>
> Steve
>
>
>
>
> -----Original Message-----
> From: Dan Bostan [mailto:dbostan@xxxxxxxxx]
> Sent: Friday, March 25, 2005 2:07 PM
> To: scott@xxxxxxxxxxxxx; Santangelo, Steven
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: DDR Termination
>
>
> From my experience, the parrallel termination can be
> eliminated, but only after reducing the length of
> traces and extensive simulations to make sure SI and
> timing are OK.
> As Scott said, the timing margins are smaller without
> the VTT parallel terminations.
> /dan
>
> --- Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
>> Steven
>>=20
>> The answer is: "Yes, you should be concerned."
>>=20
>> The primary reason for the parallel termination to
>> Vdd/2 is to center=20
>> the switching around Vref.  At low speeds this is
>> not critical. But at=20
>> high speed, intersymbol interference (ISI) and
>> pattern run lengths of=20
>> all zeros and all ones will eat your timing margin
>> alive.
>>=20
>> There are two reasons for series termination. The
>> first reason is to=20
>> provide a better impedance match for the drivers.=20
>> The second reason to=20
>> to provide resistive losses to de-Q resonances in
>> the channel.  DDR even=20
>> with series and parallel termination is not a well
>> damped system.  At=20
>> higher frequencies the channel resonances will kill
>> you.
>>=20
>>=20
>> best regards,
>>=20
>> scott
>>=20
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882
>> (401) 284-1827 Business
>> (401) 284-1840 Fax
>>=20
>> http://www.teraspeed.com
>>=20
>> Teraspeed=AE is the registered service mark of
>> Teraspeed Consulting Group LLC
>>=20
>>=20
>>=20
>> Santangelo, Steven wrote:
>>=20
>> >Hi,
>> >
>> >I'm looking at a DDR interface which consists of a
>> controller and a =3D
>> >single SODIMM module.  In the past we've
>> successfully simulated, built =3D
>> >and tested this interface using only series
>> terminations but have always =3D
>> >run it fairly slow, 100MHz or 133MHz.   As we crank
>> up the clock on =3D
>> >future designs I'm starting to wonder if we should
>> switch to the more =3D
>> >standard series+parallel termination scheme.  Aside
>> from the increased =3D
>> >over and undershoot and any resulting EMI issues, I
>> don't see a big =3D
>> >difference between the 2 approaches.  If anything,
>> the series only =3D
>> >approach appears to give me better noise margin due
>> to the increased =3D
>> >swing.  Should I be concerned about using the
>> series termination only =3D
>> >approach when running at higher speeds, say 166MHz
>> or 200MHz?  What =3D
>> >areas should I be concerned about?
>> >
>> >Thanks
>> >
>> >Steve
>> > =3D20
>>
>>------------------------------------------------------------------
>> >To unsubscribe from si-list:
>> >si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in
>> the Subject field
>> >
>> >or to administer your membership from a web page,
>> go to:
>> >http://www.freelists.org/webpage/si-list
>> >
>> >For help:
>> >si-list-request@xxxxxxxxxxxxx with 'help' in the
>> Subject field
>> >
>> >List FAQ wiki page is located at:
>> >              =20
>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>> >
>> >List technical documents are available at:
>> >                http://www.si-list.org
>> >
>> >List archives are viewable at:    =20
>> > http://www.freelists.org/archives/si-list
>> >or at our remote archives:
>> > http://groups.yahoo.com/group/si-list/messages
>> >Old (prior to June 6, 2001) list archives are
>> viewable at:
>> > http://www.qsl.net/wb6tpu
>> > =20
>> >
>> >
>> > =20
>> >
>>=20
>>
> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in
>> the Subject field
>>=20
>> or to administer your membership from a web page, go
>> to:
>> http://www.freelists.org/webpage/si-list
>>=20
>> For help:
>> si-list-request@xxxxxxxxxxxxx with 'help' in the
>> Subject field
>>=20
>> List FAQ wiki page is located at:
>>               =20
>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>>=20
>> List technical documents are available at:
>>                 http://www.si-list.org
>>=20
>> List archives are viewable at:    =20
>> http://www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are
>> viewable at:
>>  http://www.qsl.net/wb6tpu
>>  =20
>>=20
>>=20
>
>
> =09
> __________________________________=20
> Do you Yahoo!?=20
> Yahoo! Small Business - Try our new resources site!
> http://smallbusiness.yahoo.com/resources/=20
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
> List FAQ wiki page is located at:
>                http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
> List technical documents are available at:
>                http://www.si-list.org
>
> List archives are viewable at:
> http://www.freelists.org/archives/si-list
> or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
>  http://www.qsl.net/wb6tpu
>
>

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: