[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 8 Dec 2001 15:03:33 -0800
The devil is in the details. In my simplisitic view of power
distribution problems, I always seperate the cases between
core and I/O power distribution noise.
In the former, switching activities inside the die creats
the load and the power supply has to somehow provide a low
impedance path to provide the power to the internal load.
This is what I refer to as classical decoupling, power planes
analysis etc. If you buy into my Japanese garden water bucket
analogy, the transfer between package and PCB occurs somewhere
around 100MHz. Like Larry said, the bucket gets faster and
smaller towards the die and larger and slower towards the power
supply. A corolllary of the analogy is if you improved the
response of the upstream (power supply side) through Zycon or
zillions of decoupling capacitors, you have to improved
the corresponding respond downstream (package/die side)
to get real benefit from it. If the package is aready
at the limit in terms of pins, planes or decoupling capacitane
at 100MHz or below, there is no additional benefit you can
get from the Zycon plane in PCB above 100MHz. Yet another
corollary of the analogy is if you already have a distribution
problem on die and package, nothing you can do on the PCB
side can eliminate the problem. In neither case Zycon can't
help.
In the later, it is an asymmetrical current loop between the
I/O power (or ground) and the signal traces. It starts from the
driving end, propagate through the signal traces to either the
terminator or the receiving end and return through the power/gnd
distribution to the driving end. I am not sure if resonance is
the proper term to use. Maybe noise with a strong component at
certain frequency is a better term. Given a fixed driver edge
rate, the di/dt on the package will results in certain power/
ground bounce pattern (amplitude and duration). Such bouncing
pattern will propagate out through the signal (not the power/gnd)
as ringing. I think decoupling is the wrong concept or term to
use here. You can't "decouple" a signal trace to power/ground
other than its natural transmission line characteristic define
by the impedance control stackup. Low impedance path for return
current is a better analogy. Managing the return current flow
is more important than any decoupling strategy you can create.
Some mentioned using the decoupling plane next to the power
plane that sandwich the signal trace as image current return.
I think the current flowing on both side of that power plane
has significant isolation between they (even though the are
flowing in the same plane but on different sides). It is still
not as low impedance as the plane capacitance between the
power/ground planes sandwiching the signals. If you have
to throw in the extra plane and extra cost to have those
< 2mil planes. You mind as well make sure the referencing
plane is the I/O power plane. It will save you the cost
of the extra plane pairs and it will also be the
lowest imedance path for the return current.
-----Original Message-----
From: Todd Westerhoff [mailto:twester@xxxxxxxxxxx]
Sent: Friday, December 07, 2001 6:50 AM
To: chris.cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Buried Capacitance thread comments (The whole
t hing)
Can I paraphrase?
Mike - are you saying if there's a power distribution problem on the ASIC,
proper board decoupling will at least prevent resonances from affecting the
supply voltages to other parts at the PCB level?
Chris - are you saying you agree, but if the driving device has a
package-level power problem, the design is already in trouble, regardless of
whether the resonance affects other devices or not?
Todd.
Todd Westerhoff
SI Engineer - Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
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