[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)

  • From: Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 3 Dec 2001 11:03:24 -0800 (PST)

One thing is for sure: Whenever mud is thrown, everyone gets muddy.
Let's see if we can keep our comments on a technical level.  Everyone
is entitled to an opinion.  The last opinion left on the table does not
necessarily become physical law.

GHz noise definitely appears on the PCB core power and ground planes.
It is a function of frequency.  It's magnitude closely follows the
impedance profile associated with plane resonances.  Take your spectrum
analyzer and measure it as you sweep the clock frequency it you don't
believe that.  This noise will probably not cause SI problems but may
cause EMI problems depending on a lot of other factors.  Thin power
plane dielectrics definitely reduce the noise.

Some one has said that there can be no noise above 200 MHz on the PCB.
It is true that the inductance of the package attenuates the noise from
the silicon.  The chip capacitance and package inductance form a nice
low pass filter.  But how much attenuation does that filter have?  If
it has 40 dB, that is only a factor of 100.  We may have 100 watts of
power at 1 GHz on the chip and 1% escapes.  But, 1 watt of power at
1GHz loose on our PC boards is a major issue!  Several papers have been
written by authors at Sun and Georgia Tech that give both theoretical,
simulated and measured results for thin laminates.  There is no
question that they may be used to dampen a noise problem if it exits.
(In this case, problem is defined as "can't ship the product.")

Buried capacitance is not really the issue.  A much more important
property of thin laminates is the spreading inductance: the thinner the
laminate, the lower the inductance.  This is the inductance that stands
between the the uP chip and nearly all of the decoupling capacitors
everywhere on the PCB.  While it is possible to place decaps directly
under the uP package, most of the decoupled power will flow to the
processor through the inductance of the power planes.  The thinner, the
better.

The real issue is impedance.  The chip circuits want to look out to the
outside world and see a low impedance (target impedance, which is
easily calculated).  The power planes have impedance that is directly
proportional to the thickness of the dielectric between Vdd and Gnd.
The power plane impedance is in series with most all of the energy
reservoirs including faraway plane capacitance, discrete capacitors
and the VRM.  If the power planes are not low impedance, the chip is
not going to look out and see low impedance from the PCB.

Somebody seems to have a patent on buried PCB capacitance, as silly as
that may seem.  Why don't we just declare that impedance and inductance
are the important parameters for power planes?  Let's make this public
domain so that nobody gets a patent on it.  We can do that right now on
this list... :)   Power distribution, clean signal environments and EMI
performance benefit greatly from the low impedance, low inductance and
high damping properties of thin laminates.  The buried capacitance
between the planes is just an incidental benefit.  We use thin
laminates as a conduit to pipe in power, not necessarily to replace
discrete capacitors.

Istvan Novak is hosting a technical session on thin laminates at Design
Con this year.  I hope that it is well attended.

regards,
Larry Smith
Sun Microsystems

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