[SI-LIST] Re: DDR SDRAM

  • From: "D. C. Sessions" <si-list@xxxxxxxxxxxxxxxx>
  • To: "'SI-LIST'" <si-list@xxxxxxxxxxxxx>
  • Date: Sat, 8 Dec 2001 23:44:21 -0700

On Friday 07 December 2001 08:19, Peter LaFlamme wrote:
> Hi Bob,
> I am involved in a similar situation. I have not run across a lot of info on 
> SI or timing issues, however, on the Micron site there is a "designer's 
> toolkit" that offers some things that help. I found that the power calculator 
> tool is quite handy.
> Additionally, the DDR spec and addendum are mostly concerned with the timing 
> diagrams and pin-outs for the 4/8/16 bit wide devices. You may be able to 
> find more info if you look into the SDRAM stuff, since the DDR is SDRAM with 
> data registered on both
> edges of the clock. 
> 
> Let me know if you find anything additional. It would be helpful.

There's quite a bit of applications stuff at http://www.ami2.com

It makes a huge difference whether you're doing point-to-point or
bussed data.  Point-to-point is much cleaner, but there's less application
data for it.  (JC-16 is working some of that now.  Better late than never.)

It turns out that useful metrics for nonlinear (i.e. practical) drivers in
near-resonant reflected-wave applications are hard to come by, by
the way.  We're probably going to be forced to define a characterization
environment and just put a limit on jitter.

> "Khederian, Bob" wrote:
> > 
> > I am doing a design with DDR SDRAM.  I am using discrete devices, not
> > modules.  Does anyone know of some good application notes for signal
> > integrity issues on these parts.
> > 
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> 
> -- 
> Peter LaFlamme
> 
> Applied Micro Circuits Corp.
> Staff System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
> 
> 978-247-8470 phone
> 978-623-0055 Fax
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-- 
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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