[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)
- From: MikonCons@xxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 7 Dec 2001 14:51:13 EST
Todd:
You are correct on both counts. As well as reducing PCB resonances, BC
minimizes the transient power-ground voltage perturbation for +/- current
demands of any active package on the board. Whether or not the package has an
internal SSO-induced problem, the impact of any noise generated between the
power and ground planes on the board/system will be reduced by the use of BC
techniques. If the chip+package combination is most or part of the problem,
the external/PCB BC will minimize the impact on the rest of the system, but
obviously cannot solve the chip's internal problem.
Like any design, solving the (potential) problem at its source is the the
correct way. Any external correction/compensation is really a fallback patch.
Nevertheless, history has shown that EMC concerns usually take a back seat to
the functional design task (although they really are part of the total
design); therefore, building suppression techniques into the PCB (or
ultimately closing everything in a sealed box) is usually necessary for
radiated emissions.
To minimize EMI problems, burying signals internal to the PCB (i.e., avoid
microstrip for all high-speed signals) is step one.
Mike
Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843
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