[SI-LIST] Re: Buried Capacitance thread comments (The whole t hing)
- From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- To: "'larry smith'" <ldsmith@xxxxxxxxxxxxxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx, Chris Cheng <chris.cheng@xxxxxxxxxxxx>
- Date: Tue, 4 Dec 2001 12:10:51 -0800
Larry,
We all serve our masters, old and new. As such there are
things we do many times should not be discussed.
I think you are mixed up with the following,
a) Does a GHz process generate GHz core noise ? Yes.
Does all 100W of its power are running at a GHz ?
Absolutely not. As to what the frequency components
of the 100W power budget ? Those are proprietory
things that neither of us should discuss. Rest
assure they are well addressed and understood though.
b) The unfortunate fact for me having to serve
some masters that wants to ship an M1 tank with a budget
of a Honda means there are proprietory ways to meet
those reqirement at the package level with a cost
effective way. Rest assure they have been analyzed
and the most cost effective way has been designed in.
Knowingat both companies I've worked for I know I
have at least acieved a 2X improvement on the package
performance with a lower cost.
c) As to the <2mil replacing bulk caps, I am refering
to this observation. I don't think those are 1000pf caps :
>When using <2mil core, placing a single 0805 4.7uf via-in-pad bypass cap
per
>voltage plane pair, under the center of a large BGA part where the
>"recommended" bypassing is 24 0.1uf caps near the power/gnd pins works very
>well.
-----Original Message-----
From: larry smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxxxxxxx]
Sent: Tuesday, December 04, 2001 10:26 AM
To: si-list@xxxxxxxxxxxxx; chris.cheng@xxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Buried Capacitance thread comments (The whole
t hing)
Chris - You have an interesting analogy with the "Japanese garden water
irrigation" system. The analogy would be even more correct if the
water buckets near the plant were small and fast and the buckets
further away were larger and slower. The volume of water transported
remains constant. Years ago, I remember some IBM engineers discussing
a "time constant" methodology for decoupling and bringing power into a
chip. That is a time domain method of managing RC time constants of
capacitors that are further and further away from the chip. The method
can be used with good success.
I prefer a frequency domain method where the chip circuits look out and
see a managed impedance that is a function of frequency. The target
impedance is easily calculated as
Zt = Vdd x 5% / transient_current
The 5% determines the ripple that the circuits will see, choose your
own percentage. The on-chip capacitance provides current in the
shortest amount of time. It determines the power supply impedance from
the GHz region down to somewhere near 100MHz. Below that frequency,
current must come from off-chip.
In your note, you alluded to package capacitance. That is an excellent
place to put some capacitance. It is off-chip, but comes before the
package/socket/PCB inductance (let's say that we are on the chip
looking out). I recently purchased a 900MHz AMD processor and mother
board at our local computer supply house for under $250. The uP was
flip-chip mounted on a ceramic package (CPGA). On top of the package
there was 14 capacitors (3 IDC's and 11 x 0612's, at least two
different types). Clearly, the AMD guys understand the value of
capacitors on the package surface for managing power distribution.
You also discussed the economics of package capacitors vs 2-mil core
PCB layers. Yes, this is the economic trade-off. But, in order use
package capacitors, you have to be willing to hook them up. This means
a low impedance (inductance and resistance) path from the chip pins to
the package caps. It means that the chip and package must be
engineered to enable the power hookup. Because of the cost and
intellectual property issues involved with thin PCB cores, the
motivation is certainly there to design a system that makes good use of
package capacitors.
I don't think anybody has ever claimed that "<2 mil core can eliminate
large amount of bulk caps." A 2 mil core has about 500pF/square inch
and can eliminate a lot of caps that are 1000pF and below. The thin
cores can be useful in solving EMI problems. It is quite possible to
combine enough discrete capacitors on the PCB to create a low impedance
at high frequency (more than 100 MHz). But there is little point in
doing that unless you have a low impedance (thin PCB core) set of power
planes to bring the low impedance to the chip.
There are lots of ways to build a power system. Thin core PCB's are a
valuable resource. Capacitors on the package are a valuable resource.
Material suppliers play games with their prices and licensing
agreements. In the end, we SI'ers will settle in on the most economic
solution given the product requirements and market conditions.
regards,
Larry Smith
Sun Microsystems
> Delivered-To: si-list@xxxxxxxxxxxxx
> From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole t
hing)
> Date: Mon, 3 Dec 2001 15:36:41 -0800
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> X-original-sender: chris.cheng@xxxxxxxxxxxx
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>
>
> Larry,
> Glad you point out the power impedance distribution issue.
> I always have this simplistic view of power distribution
> as those that starts with
> a water tap, fill the first bucket up, when its full it
> flips and fill the next one, repeated until the last
> bucket water the plant. As such you can do similar analysis
> on power distribution of highspeed IC. Starting with the
> appropriate on die switching activities you can progressively
> simulate the effect of decoupling all the way to the power
> pod that supply the IC. In my opinion, the optimal design
> will be starting with the closest decoupling cap (most
> likely on die) observe the current in and out of the caps
> (if the current is +ve, the cap is helping out the decoupling
> if the current is -ve, the cap is starting to deplete and
> need a bigger bulkier capacitor upstream towards the power
> supply) I consider this methodology as the economics of
> decoupling, used the minimal amount of decoupling to get
> the job done with the least cost. There is however one
> more complication. Unlike the garden analogy, the way the
> bucket (caps) get filled and discharged is heavily dependent
> on the type of caps and it also depends on their location,
> the way charge flow between the buckets. Based on most of
> the analysis I've done, the appropriate cut off point between
> the package and the PCB happens between 100-200MHz. Of course
> this is not a fixed rule, if the buckets downstream (towards the
> die) is inappropriately size, you need more buckets (caps) and
> better flow paths (between the caps). I think a better solution
> to fix the problem should come from fixing the downstream caps
> and as package designers, it is important for them to understand
> (in a case by case bases) what is the die and package interaction
> on decoupling issues. What you have suggested seems to be fixing
> the flow path upstream at the PCB, while I believe my opinion is
> doing the same upstream (on die and on package). Its the economics
> of decoupling. Both will work but at a cost. Is it more expensive
> to lower the impedance path on a smaller package with less caps or
> is it more expensive to pay for the 2 mil core planes and more
> caps on the PCB ?
>
> As for the claim that <2 mil core can eliminate large amount of
> bulk caps. One has to consider whether the ESL,pad and via inductance
> of the decoupling caps dominates the impedance path or the much
> lower mutual plane inductance has a more profound effect. I could
> be wrong but I believe the former is more pronounced.
>
>
> -----Original Message-----
> From: Larry Smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxx]
> Sent: Monday, December 03, 2001 11:03 AM
> To: si-list@xxxxxxxxxxxxx
> Cc: michael.freda@xxxxxxxxxxx
> Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole t
> hing)
>
>
>
> One thing is for sure: Whenever mud is thrown, everyone gets muddy.
> Let's see if we can keep our comments on a technical level. Everyone
> is entitled to an opinion. The last opinion left on the table does not
> necessarily become physical law.
>
> GHz noise definitely appears on the PCB core power and ground planes.
> It is a function of frequency. It's magnitude closely follows the
> impedance profile associated with plane resonances. Take your spectrum
> analyzer and measure it as you sweep the clock frequency it you don't
> believe that. This noise will probably not cause SI problems but may
> cause EMI problems depending on a lot of other factors. Thin power
> plane dielectrics definitely reduce the noise.
>
> Some one has said that there can be no noise above 200 MHz on the PCB.
> It is true that the inductance of the package attenuates the noise from
> the silicon. The chip capacitance and package inductance form a nice
> low pass filter. But how much attenuation does that filter have? If
> it has 40 dB, that is only a factor of 100. We may have 100 watts of
> power at 1 GHz on the chip and 1% escapes. But, 1 watt of power at
> 1GHz loose on our PC boards is a major issue! Several papers have been
> written by authors at Sun and Georgia Tech that give both theoretical,
> simulated and measured results for thin laminates. There is no
> question that they may be used to dampen a noise problem if it exits.
> (In this case, problem is defined as "can't ship the product.")
>
> Buried capacitance is not really the issue. A much more important
> property of thin laminates is the spreading inductance: the thinner the
> laminate, the lower the inductance. This is the inductance that stands
> between the the uP chip and nearly all of the decoupling capacitors
> everywhere on the PCB. While it is possible to place decaps directly
> under the uP package, most of the decoupled power will flow to the
> processor through the inductance of the power planes. The thinner, the
> better.
>
> The real issue is impedance. The chip circuits want to look out to the
> outside world and see a low impedance (target impedance, which is
> easily calculated). The power planes have impedance that is directly
> proportional to the thickness of the dielectric between Vdd and Gnd.
> The power plane impedance is in series with most all of the energy
> reservoirs including faraway plane capacitance, discrete capacitors
> and the VRM. If the power planes are not low impedance, the chip is
> not going to look out and see low impedance from the PCB.
>
> Somebody seems to have a patent on buried PCB capacitance, as silly as
> that may seem. Why don't we just declare that impedance and inductance
> are the important parameters for power planes? Let's make this public
> domain so that nobody gets a patent on it. We can do that right now on
> this list... :) Power distribution, clean signal environments and EMI
> performance benefit greatly from the low impedance, low inductance and
> high damping properties of thin laminates. The buried capacitance
> between the planes is just an incidental benefit. We use thin
> laminates as a conduit to pipe in power, not necessarily to replace
> discrete capacitors.
>
> Istvan Novak is hosting a technical session on thin laminates at Design
> Con this year. I hope that it is well attended.
>
> regards,
> Larry Smith
> Sun Microsystems
>
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