[SI-LIST] Re: Article discussion on bad packages - core
- From: steve weir <weirsp@xxxxxxxxxx>
- To: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>, <Larry.Smith@xxxxxxx>
- Date: Thu, 06 Jan 2005 07:28:08 -0800
Istvan, I think that we agree on a number of points. Not the least of
which are the issues of: cavity resonances, signal return bypass versus
power distribution, a preference for the big "V" bypass strategy, spatial
variations of PDN impedance.
I have never been very warm to the closely spaced SRF method that Larry and
company developed, due primarily to the design and manufacturing
complications. However, my models do show that it can reduce total
capacitor count by about 20% for the same impedance close. At the
capacitor attachment to the planes, it also tends to close at about 70 - 75
degrees versus a virtual 90 degrees for the big "V" that I prefer. I do
note that phase advantage may never make it to the IC package where it
could do some good. I was intrigued by some of Larry's comments that
implied perhaps someone had found a recipe to close at a relatively low
phase without adding a whole lot of capacitors. If such a recipe exists it
would help with the AR resonance at the package internal cut-off.
Larry's comments had me revisit my models of the closely spaced SRF method
to see how it might perform with low inductance capacitors, X2Y, IDC, LICC,
etc. I have come up with what I think are some interesting data
points. Assuming a 150pH partial inductance for a well-designed short
attachment via, and 500pH for a typical 0603 MLCC cap, and 100pH for a low
inductance cap of the user's choice, for that 1mohm network we have been
discussing, I get:
Big "V" in conventional caps: 800pH / mounted cap / 1.6pH budget = 500
capacitors, 1000 vias, 90 deg. closing phase.
X^2.2 method, 429 capacitors, 858 vias, 73 deg. closing phase.
Big "V" in low inductance caps: 200pH / mounted cap ( 6 via X2Y, or 8 via
IDC ), 126 low L caps, + 3 10uF conventional caps to cover the low end, 129
caps total, 762 vias, 90 deg closing phase.
X^2.2 method variant using a combination of low inductance and conventional
caps, 84 low inductance, + 42 conventional caps again for the low end, 126
caps total, 588 vias, 70 degrees closing phase at 100MHz.
Now, as much as I am not very happy about the number of different capacitor
values required by the X^2.2 method or variations on it, removing 23% of
the vias is something that could prove quite compelling to an OEM. That
needs to be weighed against the assumption that I also tend to challenge,
and you point out that the current vs. frequency profile is flat versus
having a peak in the middle where the big "V" happens to provide superior
insertion loss. So, my upshot here is that while I firmly remain a strong
proponent of the big "V" approach, I respect that the X^2.2 approach can
provide specific advantages in exchange for its specific caveats.
A point that we vehemently agree upon is the spatial variation in impedance
of the bypassed PCB, particularly high performance PCBs. I think this is
poorly understood by many to their own peril. I think it is very dangerous
to discuss a PCB impedance as a global, homogenous constant, when for
anything but low performance boards, it is anything but.
I agree that damping doesn't provide much of a justification for leakage
current. But if we are stuck with high leakage current, at least it helps
offset a potential major headache.
Regards,
Steve.
At 09:33 AM 1/6/2005 -0500, Istvan NOVAK wrote:
>Steve,
>
> > BTW, have you done any tolerancing work to examine how far beyond the
> > package cut-off you need to hold phase? Without having run specific
> > numbers, my feel for it is that 2X should be enough to stay out of
>trouble.
>
>With the risk that some may feel that I am muddying the water again -:),
>let me add a few points.
>
>Dependent on the system partitioning and chosen
>technology, the requirements at various points along the PDN may
>be very different. Core power distribution seems to be an easy
>example, because often times it is a single point of load. Still, however,
>at various points of a single-load core PDN, the impedance
>requirements may be different, and at the different locations the
>required/achieved frequency characteristics may be different. The
>on-die capacitance cumulatively has a much lower resistance than
>the required impedance on the board. And it is rightly so, because
>the highest di/dt and the highest cumulative peak current occurs on
>the silicon. As we move out from the silicon to the package, and
>further to the board, eventually the transient peaks, which are in
>the order of the clock period, are averaged out, and the required
>impedance goes up to a mid-frequency value. At very low
>frequencies (say low 100Hz to kHz range), the impedance requirement
>may go down again, because even if we power down or power up the
>silicon gradually, at low frequencies we will get the full maximum - minimum
>current step. Increasing leakage current definitely helps in this, but
>unfortunately this looks to me like a step backwards towards vacuum tubes...
>
>Besides the different impedance requirements at various frequency
>ranges, location along the PDN also makes a difference. As it
>was poiinted out on this thread, well above the cutoff frequency of
>the package, the board impedance could be virtually anything and
>we could still guarantee the required impedance at the silicon. While
>this is true, additional considerations are needed if 1) the core plane
>shapes have large open areas not filled with the chips and capacitors
>and/or 2) if the core plane shape is used as a return plane for sensitive
>signals. Case 1) may be an EMI risk; unloaded and unterminated plane
>areas resonate and any small leakage of core clock or core signal
>may get amplified by the resonance peaks. Case 2) is an SI risk
>for the sensitive signals; even though a high level of noise above
>the package cutoff frequency is OK for the core it feeds, it may
>be bad for the signals.
>
>As you said, maintaining resistive board (self)impedance at the milliohm
>level gets very tough above 10MHz, but with the added complications
>outlined above, this may not be the highest priority to achieve.
>Good board-level PDN for both core and IO can also be achieved with
>just a single value of ceramic bypass capacitor, let it be low-ESR or
>high-ESR type.
>
>Regards,
>
>Istvan Novak
>SUN Microsystems
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