Posts for si-list, 01-2005

Browse: Last Month: 12-2004 Main Archive Page Next Month: 02-2005

» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] SI Employment Opportunity: Posting -
» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] Re: Propagation delay question -
» [SI-LIST] Propagation delay question -
» [SI-LIST] Input Clock phase noise and TX eye closurein SERDES -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] UNSUBSCRIBE -
» [SI-LIST] Re: Coupled & Lossy Line Model Validation Structure -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] routing mini usb conn. -
» [SI-LIST] help in split planes for analog & digital pins of ADC -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: EM Simulation, Chipsets & USB -
» [SI-LIST] EM Simulation, Chipsets & USB -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: Coupled & Lossy Line Model Validation Structure -
» [SI-LIST] Coupled & Lossy Line Model Validation Structure -
» [SI-LIST] Re: PLD programming data -
» [SI-LIST] Re: Is there a latest version of s2ibis2 software to subtract both clamps from the pull up and pull down waveforms in an IBIS model -
» [SI-LIST] Re: PLD programming data -
» [SI-LIST] Re: PLD programming data -
» [SI-LIST] Re: PLD programming data -
» [SI-LIST] Re: PLD programming data -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] PLD programming data -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] Re: subscribe: bulk capacitor -
» [SI-LIST] subscribe: bulk capacitor -
» [SI-LIST] Re: Is there a latest version of s2ibis2 software to subtract both clamps from the pull up and pull down waveforms in an IBIS model -
» [SI-LIST] Is there a latest version of s2ibis2 software to subtract both clamps from the pull up and pull down waveforms in an IBIS model -
» [SI-LIST] Is there a latest version of s2ibis2 software to subtract both clamps from the pull up and pull down waveforms in an IBIS model -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: subscribe: bypass capacitor -
» [SI-LIST] Re: subscribe: the bypass and decouple capacitor -
» [SI-LIST] subscribe: bypass capacitor -
» [SI-LIST] Re: subscribe: the bypass and decouple capacitor -
» [SI-LIST] Re: subscribe: the bypass and decouple capacitor -
» [SI-LIST] subscribe: the bypass and decouple capacitor -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Deadline Reminder SPI 2005 -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: drive ability -
» [SI-LIST] Re: Fw: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] FW: Re: subscribe: drive ability -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] Re: capacitor impedance in time domain -
» [SI-LIST] capacitor impedance in time domain -
» [SI-LIST] Re: Fw: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Re: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Re: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Re: subscribe: drive ability -
» [SI-LIST] subscribe: drive ability -
» [SI-LIST] Re: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Fw: Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Transmission line impedance is related to signal switching frequency ? -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Analog Signal Integrity opening -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: Plane breaks - Diff pair crossing -
» [SI-LIST] Re: Plane breaks - Benchmark report download -
» [SI-LIST] Plane breaks - Benchmark report download -
» [SI-LIST] Re: Plane breaks - Diff pair crossing -
» [SI-LIST] Re: need SPICE model -
» [SI-LIST] Re: need SPICE model -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: Plane breaks - Diff pair crossing -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Re: Plane breaks - Presentation download -
» [SI-LIST] Plane breaks - Presentation download -
» [SI-LIST] need SPICE model -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Crosstalk in High-Speed Interconnects -
» [SI-LIST] rail noise -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Crosstalk in High-Speed Interconnects -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Crosstalk in High-Speed Interconnects -
» [SI-LIST] Re: Crosstalk in High-Speed Interconnects -
» [SI-LIST] Crosstalk in High-Speed Interconnects -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Trace skew matching, common mode conversion and laminate weave ... oh my! -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: serpentine routing -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Thermal reliefs -
» [SI-LIST] Re: serpentine routing -
» [SI-LIST] serpentine routing -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] PCB Thermal Analysis -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Just a test. Pls ignore -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Any HSPICE Course in Bay Area? -
» [SI-LIST] Any HSPICE Course in Bay Area? -
» [SI-LIST] Re: Thermal reliefs -
» [SI-LIST] Re: Orcad Layout to Mentor Graphics PADS -
» [SI-LIST] Re: Thermal reliefs -
» [SI-LIST] High speed routing -
» [SI-LIST] Thermal reliefs -
» [SI-LIST] Re: Orcad Layout to Mentor Graphics PADS -
» [SI-LIST] Signal Integrity Basics -
» [SI-LIST] Re: risetime effects of plane breaks - microstrip radiation -
» [SI-LIST] Re: risetime effects of plane breaks - microstrip radiation -
» [SI-LIST] Orcad Layout to Mentor Graphics PADS -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: help driving a diff clk to ADC -
» [SI-LIST] Re: what is quiet line noise -
» [SI-LIST] help driving a diff clk to ADC -
» [SI-LIST] Re: How to analyze jitter of data -
» [SI-LIST] Re: How to analyze jitter of data -
» [SI-LIST] Re: How to analyze jitter of data -
» [SI-LIST] Re: How to analyze jitter of data -
» [SI-LIST] [***SPAM*** Score/Req: 05.60/05.00] question -
» [SI-LIST] How to analyze jitter of data -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Coplanar waveguide propagation delay -
» [SI-LIST] Extracta script -
» [SI-LIST] Re: what is quiet line noise -
» [SI-LIST] Re: Coplanar waveguide propagation delay -
» [SI-LIST] what is quiet line noise -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: Coplanar waveguide propagation delay -
» [SI-LIST] Re: Coplanar waveguide propagation delay -
» [SI-LIST] Re: About High side Switching. -
» [SI-LIST] Coplanar waveguide propagation delay -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: About High side Switching. -
» [SI-LIST] About High side Switching. -
» [SI-LIST] European IBIS Summit At DATe 2005 - Second Call for Papers/Call for Participation -
» [SI-LIST] Berkeley SPICE to Intusoft SPICE question -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: controlled impedance requirements -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: CRT DAC video filter -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] High Dielectric Constant Laminate Materials -
» [SI-LIST] Re: controlled impedance requirements -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: TDR Resolution -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] SI Job posting -
» [SI-LIST] TDR Resolution -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: controlled impedance requirements -
» [SI-LIST] controlled impedance requirements -
» [SI-LIST] Re: searching for analog n mixed signal design tools -
» [SI-LIST] Re: searching for analog n mixed signal design tools -
» [SI-LIST] Re: searching for analog n mixed signal design tools -
» [SI-LIST] searching for analog n mixed signal design tools -
» [SI-LIST] Re: Softwares for High-Speed Signal Integrity -
» [SI-LIST] Re: Softwares for High-Speed Signal Integrity -
» [SI-LIST] IC power/ground and I/O noise measurements -
» [SI-LIST] CRT DAC video filter -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Softwares for High-Speed Signal Integrity -
» [SI-LIST] Softwares for High-Speed Signal Integrity -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: HSPICE Capable Tools -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] SI job openning -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Re: HSPICE Capable Tools -
» [SI-LIST] Re: HSPICE Capable Tools -
» [SI-LIST] HSPICE Capable Tools -
» [SI-LIST] Re: voltage regulator -
» [SI-LIST] A New SI Web Resource -
» [SI-LIST] voltage regulator -
» [SI-LIST] Differential Pairs Tip&Ring Cross talk -
» [SI-LIST] Re: Differential Network Analyzer -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Re: Differential Netwrok Analyzer -
» [SI-LIST] Re: job posting -
» [SI-LIST] Differential Netwrok Analyzer -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] job posting -
» [SI-LIST] Re: Layoff -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: [SI_LIST] Bondwire RLC Number -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: Bondwire RLC Number -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Bondwire RLC Number -
» [SI-LIST] Re: RMCEMC January meeting announcement -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Layoff -
» [SI-LIST] Reminder SPI 2005 - Call for Papers -
» [SI-LIST] Re: Differencial pairs signals - reference plan -
» [SI-LIST] Differencial pairs signals - reference plan -
» [SI-LIST] Re: Low Dielectric material for PCB manufacturing - help needed -
» [SI-LIST] Re: Low Dielectric material for PCB manufacturing - help needed -
» [SI-LIST] Low Dielectric material for PCB manufacturing - help needed -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: RMCEMC January meeting announcement -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: How to define the value of capacitor -
» [SI-LIST] Re: Windows-based schematic editors -
» [SI-LIST] How to define the value of capacitor -
» [SI-LIST] Re: Windows-based schematic editors -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] RMCEMC January meeting announcement -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: some help needed -
» [SI-LIST] Re: some help needed -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: risetime effects of plane breaks -
» [SI-LIST] Re: some help needed -
» [SI-LIST] risetime effects of plane breaks -
» [SI-LIST] Re: some help needed -
» [SI-LIST] Re: some help needed -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: 3D .mcm geometry viewers -
» [SI-LIST] some help needed -
» [SI-LIST] Re: CAN Edge Rates -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - I/O -
» [SI-LIST] Re: Article discussion on bad packages - I/O -
» [SI-LIST] Re: Reference when interconnect is an S-parameter file -
» [SI-LIST] Re: Article discussion on bad packages - I/O -
» [SI-LIST] January 11, 2005 IEEE-EMCS Santa Clara Valley Chapter Meeting Notice -
» [SI-LIST] Reference when interconnect is an S-parameter file -
» [SI-LIST] Re: Article discussion on bad packages - I/O and core -
» [SI-LIST] Re: modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] Re: modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] Capacitor with DWV 1500V -
» [SI-LIST] Re: modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] [SI-LIST]Kelvin Connection -
» [SI-LIST] Re: Spacing rules for reduction of cross talk -
» [SI-LIST] Spacing rules for reduction of cross talk -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] What is FailSafe/Non-Failsafe ESD. -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: 3D .mcm geometry viewers -
» [SI-LIST] 3D .mcm geometry viewers -
» [SI-LIST] Bad packages, core power, SSO and IBIS -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] CAN Edge Rates -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Inductance of a rectangular cross section over a ground plane? -
» [SI-LIST] Inductance of a rectangular cross section over a ground plane? -
» [SI-LIST] Re: Designcon pointer -
» [SI-LIST] Re: Article discussion on bad packages - core powermeasurments -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core powermeasurments -
» [SI-LIST] Re: Article discussion on bad packages - core power measurments -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] Designcon pointer -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] CheckList Manager - Freeware - (Initial Beta Release) design to make managing checklists, their import, signoff, and proofing easier -
» [SI-LIST] Re: 2-layer PCB Guidelines -
» [SI-LIST] Re: Article discussion on bad packages - core -
» [SI-LIST] 2-layer PCB Guidelines -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] Re: modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] modeling for tantalum capacitors and aluminium electrolytic capacitors -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] 'low or no-cost' spice resources -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Speakers sought for Santa Clara EMC Society -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Article discussion on bad packages -
» [SI-LIST] Re: Wishing All A Happy n Prosperous New Year 2004 -