[SI-LIST] Re: Article discussion on bad packages - core
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Jeremy Plunkett <jeremy@xxxxxxxxxxxxxxx>
- Date: Sun, 09 Jan 2005 22:36:44 -0500
Jeremy,
If you are in an industry segments such that for your boards blind vias
come almost no extra cost,
they can really improve on inductance. Some generic considerations,
which also have to
be factored in:
- blind-via connection of bypass caps is the most effective for the
overall layout if the primary power
signal-return power plane are the two planes close to the surface we
connect with the blind vias. If
we have additional plane layers in the stackup serving the same purpose,
we still may require extra
through holes to do the proper stitching.
- though via diameter is in the LN() function for its inductance, still,
the usually smaller diameter blind
vias will somewhat increase the partial self inductance with respect to
through holes
- through-holes (assuming we dont put them INTO the capacitor pads) not
only will result in
somewhat higher overall inductance, but also the inductance versus
frequency variation will
be more
Regarding the placement of capacitors, as usual, it all depends... Yes,
if the construction of
the board and package assembly (plus your manufacturing processes) allow
you to put
capacitors right across adjacent power/ground pads on the back side of
the board, it is
electrically attractive. There could be several reasons, however, why
you could not do it,
in which case the next best is to place them next to the chip footprint
and then connect them
horizontally with planes.
Regards,
Istvan Novak
SUN MIcrosystems
Jeremy Plunkett wrote:
>Hmmm...hate to expose myself reading SI list this late on a Friday night,
>but I have to point out that if Istvan is using blind vias he can probably
>place them in a row under the part between the two pads, alternating VDD GND
>VDD GND and get pretty much the lowest inductance possible for a cap with 2
>terminals connecting to buried planes.
>
>On the other hand if these are caps on the bottom of a PCB under a BGA
>pinfield, probably the best way to go is make the bottom layer (outer, 2+
>mils thick after plating) VDD and the next one up GND, in which case you'd
>put the blind vias in the GND pad and improve your mounted inductance even
>further.
>
>Actually Istvan, I'm curious how much you end up gaining with the blind vias
>in this situation, since you'll need through-hole vias to get the power up
>to the processor on the other side of the board anyway. These thru vias
>should already be all over the place in a VDD/GND checkerboard, is it really
>worth removing any of them to place pads for 0306's and microvias, when you
>could just pack the area with 0402's placed between the thru vias and cut
>the plane spreading inductance out of the picture completely?
>
>Regards,
>Jeremy
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of steve weir
>Sent: Thursday, January 06, 2005 8:04 PM
>To: Istvan NOVAK
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Article discussion on bad packages - core
>
>
>At 10:59 PM 1/6/2005 -0500, Istvan NOVAK wrote:
>
>
>>Steve,
>>
>>
>>
>>>>>At the
>>>>>capacitor attachment to the planes, it also tends to close at
>>>>>about
>>>>>
>>>>>
>>70 -
>>
>>
>>>>75
>>>>
>>>>
>>>>>degrees versus a virtual 90 degrees for the big "V" that I
>>>>>prefer.
>>>>>
>>>>>
>>>>I may miss here something; do you refer to the phase of impedance
>>>>of the lumped parallel capacitors at a fixed, say 100MHz?
>>>>
>>>>
>>>Yes, if we look at the phase for the network at the capacitor
>>>attachment ring ( really rings for a beast with 400 some odd caps ),
>>>it varies from -90degrees at low frequency to +90 degrees well above
>>>the close. We had been discussing that it is desirable to cross the
>>>package cut-off near 0 degrees which it is if it were feasible to do
>>>at little or no additonal cost. The issue is feasibility. I don't
>>>know of a way to get there without adding a monstrous quantity of
>>>additional caps. If you have a
>>>
>>>
>>way,
>>
>>
>>>you have me beat.
>>>
>>>
>>In your second example below (X^2.2 method, 429 capacitors, 858 vias,
>>73 deg. closing phase), do you look at the phase at 100MHz? What is
>>the highest SRF of the smallest-value capacitor?
>>
>>
>
>Yes, that is correct. The mounted SRF was 76MHz for the smallest
>capacitance in the X2Y group.
>
>
>
>
>>>>>Big "V" in conventional caps: 800pH / mounted cap / 1.6pH
>>>>>budget =
>>>>>
>>>>>
>>500
>>
>>
>>>>>capacitors, 1000 vias, 90 deg. closing phase.
>>>>>
>>>>>X^2.2 method, 429 capacitors, 858 vias, 73 deg. closing phase.
>>>>>
>>>>>Big "V" in low inductance caps: 200pH / mounted cap ( 6 via
>>>>>X2Y, or 8
>>>>>
>>>>>
>>via
>>
>>
>>>>>IDC ), 126 low L caps, + 3 10uF conventional caps to cover the
>>>>>low
>>>>>
>>>>>
>>end,
>>
>>
>>>>129
>>>>
>>>>
>>>>>caps total, 762 vias, 90 deg closing phase.
>>>>>
>>>>>X^2.2 method variant using a combination of low inductance and
>>>>>
>>>>>
>>>>conventional
>>>>
>>>>
>>>>>caps, 84 low inductance, + 42 conventional caps again for the
>>>>>low end,
>>>>>
>>>>>
>>126
>>
>>
>>>>>caps total, 588 vias, 70 degrees closing phase at 100MHz.
>>>>>
>>>>>
>>>>The above options are possible, but you could continue the list for
>>>>instance with another implementation of the big "V" with 'regular'
>>>>low-inductance capacitors. 0508 or 0306 parts with four
>>>>through-hole vias give you 200-300pH and a microfarad capacitance
>>>>minimum per piece. 125 caps of the 200pH kind with only 4*125=500
>>>>vias total give you the 1.6pH inductance you need and more than
>>>>100uF capacitance, so you
>>>>
>>>>
>>dont
>>
>>
>>>>need
>>>>10uF ceramics.
>>>>
>>>>
>>>Well, the devil is in what the actual numbers really are. 200pH to
>>>300pH is quite a wide relative spread. 125 pcs. at 200pH would just
>>>do it, but 300pH would require 185 parts, and more like 740 vias.
>>>The capacitance needed to reach down to 1MHz is 160uF. The big "V"
>>>case listed above was 126X1uF + 3x10uF. It looks like for your
>>>200pH case that is still required, whereas in the 300pH it is not.
>>>The good news for the 200pH
>>>
>>>
>>case
>>
>>
>>>is that with 126X1uF caps, there will not be a problem with an AR
>>>peak transitioning from the 10uF caps.
>>>
>>>
>>>
>>Agree that 200-300pH is a large range, moreover if we want to compare
>>inductance numbers for the same part in various applications, layout
>>and stackup details will also matter. I am curious: next to126*1uF
>>caps, did you find the 3*10uF parts being useful?
>>
>>
>
>Well, if we neglect the extra 30uF, the model shows we blow target |Z| by
>about 20% at the low-end. So to avoid any specmanship, I built the models
>to meet the spec in each configuration, end to end.
>
>
>
>
>>>>>Now, as much as I am not very happy about the number of
>>>>>different
>>>>>
>>>>>
>>>>capacitor
>>>>
>>>>
>>>>>values required by the X^2.2 method or variations on it,
>>>>>removing 23%
>>>>>
>>>>>
>>of
>>
>>
>>>>>the vias is something that could prove quite compelling to an
>>>>>OEM.
>>>>>
>>>>>
>>>>This depends on the technology we use. If we use blind vias to
>>>>hook up capacitors, and the planes we connect to are the second and
>>>>third layers below the surface, we can hook up both sides of the
>>>>capacitors with blind vias. Blind vias in pads are perfectly safe
>>>>today, you dont even need to plug them. Blind vias add some extra
>>>>cost, BUT 1) you do not block any routing layers further inside the
>>>>stackup, so this is even better than any of the options
>>>>listed above, and 2) when you compare the area needed for one capacitor
>>>>
>>>>
>>with
>>
>>
>>>>through-hole connection versus blind-vias-in-pad connection, the
>>>>cost reduction because of the savings in board area will eventually
>>>>make many applications with blind vias cheaper.
>>>>
>>>>
>>>Well, you may find a number of people who object to the cost of a
>>>blind
>>>
>>>
>>via
>>
>>
>>>process. In a high-end product like a server, that may be moot, and I
>>>fully concede that as a component that needs that qty of bypass caps
>>>will have other demanding requirments that may well prove that the
>>>lowest cost component, or process, does not yield the lowest cost
>>>assembly. I think this needs to be evaluated on a case by case
>>>basis. But you do raise a very worthwhile point.
>>>
>>>
>>Absolutely agree, it depends on the industry segment.
>>
>>
>>
>>>I am unclear as to why you seem to conclude that blind vias are
>>>restricted to either conventional capacitors, or the big "V"
>>>configuration. If we
>>>
>>>
>>are
>>
>>
>>>willing to use blind vias, we can see inductance gains with
>>>conventional, reverse geometry, X2Y, or IDC capacitor attachments
>>>and gain against component count needed at the high frequency end
>>>whether we go with big
>>>
>>>
>>"V"
>>
>>
>>>or x^2.2.
>>>
>>>
>>>
>>I did not mean to conclude that blind vias are restricted to certain
>>kind of capacitors, and I agree that a 'better' via arrangement can
>>further improve onb the inductance
>>of low-inductance capacitors as well. Note that the 200-300pH inductance
>>values for
>>the above example was with standard four-via connections.
>>
>>
>
>I think that is a good point. Now, let's suppose 200pH is the right number
>for the 0306s. Larry's x^2.2 method would still be perfectly valid and
>should reduce the number of capacitors needed by about 20%, but of course
>with the caveats that approach carries.
>
>The data that I have collected on 0306 w/ 4 vias has never matched, nor
>bested X2Y 0603 with 6 vias. The useful FOM I think is whether the X2Y w/
>6 vias comes out at 0.67 or less the mounted inductance of an 0306 for any
>particular situation that we wish to consider. I presume that you are
>placing your vias off the long axis ends as Jeremy has repeatedly suggested.
>
>Regards,
>
>
>Steve
>
>
>
>>Best regards,
>>
>>Istvan Novak
>>SUN Microsystems
>>
>>
>
>
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