[SI-LIST] Re: Article discussion on bad packages - core
- From: Hal Murray <hmurray@xxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 05 Jan 2005 01:55:32 -0800
> The most crucial piece of information from the chip manufacturer is
> the maximum and minimum currents that can be drawn from the PCB PDS.
> This establishes the dI or transient current that the PCB must supply.
> The rise time (dt) is determined by the low pass filter associated
> with the chip/package resonant frequency. Generally, customer code
> will determine the current waveform and therefor the frequency profile
> of the current drawn by the chip, so I don't believe it is fair to ask
> chip vendors for the power spectrum. However, they should be
> obligated to give their customers the maximum and minimum current that
> their chip will ever draw. The minium I is probably determined by
> sleep mode and power saving states.
Is is possible to give useful numbers for min/max currents on modern chips?
Consider a CPU: What code is it running?
Consider a FPGA: A nasty design can use many times the normal peak current
for a short burst without cooking itself. (Adjust duty cycle to keep
temperature reasonable.)
I occasionally scheme about writing some code that would try to go from min
to max power usage and adjust the timing to see if I can provoke troubles in
the PDS. Or something else will break. This seems like a generally nasty
sort of code to have in your toolbox.
I'm thinking of something like keep all memories active for N cycles, then do
nothing for N cycles. Repeat for a while, then try the next N. Finding the
really nasty cases would probably take help from one of the chip/system
designers/architects. How do you keep all the ALUs and memories busy?
Maybe the leakage through thin oxides will save us by making the min current
large enough so that the ratio of min:max is reasonable. :)
Worst case might be coming out of reset.
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