[SI-LIST] Re: AC Coupled Signals

• From: "Jeon, Tae-Kwang" <Tae-Kwang.Jeon@xxxxxxx>
• To: <si-list@xxxxxxxxxxxxx>
• Date: Tue, 25 Sep 2007 16:47:55 -0600
```Here's my thought.

If we place the discontinuity properly, we can cancel the reflections

Let Crx and Cp be load capacitance at Rx and the capacitance due to some
discontinuity, respectively.=20

Once the launched signal hit Cp first the fraction of the signal is
reflected and the rest of it will continue to flow to the load facing
Crx. Again the forwarding signal should reflect back to the launch side
once it hit the Crx. As a result, we have two reflected waveform.=20

Let's assume that the traveling time between Cp and Crx is tau. If tau
is set tweaking the placement of Cp such that tau is the half the period
of the frequency(assuming the signal is sinusoidal signal), the
reflected signal could be cancelled resulting in the negative resonance
in S11.

TK

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Tuesday, September 25, 2007 2:45 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC Coupled Signals

Let me try my hand on why position matter.

A normal passive channel is reciprocal. e.g. S12=3D3DS21 It only says =
the
=3D
off diagonal elements are symmetic. It doesn't say the diagonal elements
=3D
have to be equal. I believe this was the basis of Jeff Loyer's =3D
discussion a while ago.

The presence of the discontinuity affects the S11 and S22 dramatically =
=3D
different based on whether it is close to the Tx or Rx.

In the presences of imperfect loading on the Rx side, it is the =3D

Thus position makes a difference. i.e. we are tuning the S22 with the =
=3D

QED

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Tuesday, September 25, 2007 1:35 PM
To: Jory McKinley
Cc: Stephen Zinck; Scott McMorrow; leeritchey@xxxxxxxxxxxxx;
npatel@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: AC Coupled Signals

Jory, I think this is good example of where intuitively appealing=3D20
misconceptions can seduce one into translating correlation into=3D20
causation.  If you have more ringing in one case than another, it
means=3D20
that you have set up a resonance that is more severe in the one case.
=3D20
This can easily happen as a result of any number of things going on: =
=3D20
suboptimal silicon to package launch, suboptimal IC to PCB, via
stubs,=3D20
connector transitions, etc, etc.

The very simple test is to take a VNA, a couple of sections of coax
and=3D20
a DC block.  Move the DC block between the transmit end, the junction of
=3D

the two cables, and the receiver and look at the behavior of that =
net=3D20
channel.  With good coax and connectors the channel performance =
will=3D20
change almost immeasureably.  Now go and add a coax T on one side of the
=3D

DC block.  Move that whole thing around as a unit and again the
channel=3D20
performance remains the same.  Add a second coax T on the other side
of=3D20
the DC block from the first, and again move the whole thing around.  The
=3D

results will still remain uniform.   Now if you go and move one of those
=3D

T's someplace else, then the pesky mole you're trying to whack moves and
=3D

the resonance will pop up somewhere else.  The bottom line is that
it's=3D20
resonance that we need to fight and resonance doesn't know left from =3D
right.

Regards,

Steve.
Jory McKinley wrote:
> To add to this, I will ask for release of lab data that I took =
that=3D20
> shows RX_EYE clearly improves as the AC cap/term location is =
moved=3D20
> closer to the RX.  The data indicates that even though overall channel
=3D

> loss may not be affected, the 50ps edge rates we are sending
through=3D20
> the channel are affected (in terms of time domain ringing) by the
AC=3D20
> cap/term placement.  This kind of feels right.
> -Jory
> =3D20
>
> ----- Original Message ----
> From: steve weir <weirsi@xxxxxxxxxx>
> To: Stephen Zinck <signalintegrity@xxxxxxxxxxx>
> Cc: Scott McMorrow <scott@xxxxxxxxxxxxx>; =
jory_mckinley@xxxxxxxxx;=3D20
> leeritchey@xxxxxxxxxxxxx; npatel@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Sent: Tuesday, September 25, 2007 12:52:41 PM
> Subject: Re: [SI-LIST] Re: AC Coupled Signals
>
> Steve, as far as I know where we have agreement that capacitor =3D
location
> can only affect performance where the combined capacitor and mount
> presents a discontinuity and that discontinuity is located such that =
=3D
it
> forms a resonant structure with another discontinuity in the channel.
=3D
I
> fail to see where we have moved any closer to supporting your premise
> that locating a greater proportion of fixed loss before the capacitor
> changes end to end loss than placing that same fixed loss behind it.
>
> As for lab measurements, we have these as we have characterized many
> links.  We also have extensive simulations.
>
> Regards,
>
>
> Steve.
>
> Stephen Zinck wrote:
> > Hi Steve,
> >
> > I understand your point but I actually thought Scott and I were
> > getting close. I guess I still need him to explain his statement:
> > "The only time position matters is in the face of discontinuities."
> > because this runs counter to your assertion.
> >
> > It would be good to have some concrete lab measurement results to =
=3D
back
> > either of our points up. I am sorry I don't have any.
> >
> > We agree on TDR/VNA characteristics...
> >
> > Steve
> >
> > Stephen P. Zinck
> > Interconnect Engineering Inc.
> > P.O. Box 577
> > South Berwick, ME 03908
> > Phone - (207) 384-8280
> > Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> > Web - www.interconnectengineering.com=3D20
> <http://www.interconnectengineering.com>
> >
> > ----- Original Message ----- From: "steve weir" <weirsi@xxxxxxxxxx>
> > To: <signalintegrity@xxxxxxxxxxx>
> > Cc: "Scott McMorrow" <scott@xxxxxxxxxxxxx>; =3D
<jory_mckinley@xxxxxxxxx>;
> > <leeritchey@xxxxxxxxxxxxx>; <npatel@xxxxxxxxxx>; =3D
<si-list@xxxxxxxxxxxxx>
> > Sent: Tuesday, September 25, 2007 12:24 PM
> > Subject: [SI-LIST] Re: AC Coupled Signals
> >
> >
> >> Stephen, OK so when you say "lossy" or "nonlinear" you mean=3D3D20
> >> discontinuous.  Discontinuities aggravate resonances based on
> >> specific=3D3D20
> >> structure material and geometries, in other words the distance on =
=3D
a=3D3D20
> >> centimeter or millimeter scale between discontinuities.  We =3D
have=3D3D20
> >> essentially the same opportunities for channel discontinuities at =
=3D
and
> >> in =3D3D
> >>
> >> the vicinity of the transmitter as the receiver.  So I still do not
> >> see=3D3D20
> >> a defensible basis for the offered position: that placing a =3D
capacitor
> >> at =3D3D
> >>
> >> one end of the line versus the other changes the end to end loss.
=3D20
> >> What=3D3D20
> >> matters is if wherever I place one discontinuity that it sets up a
> >> sharp =3D3D
> >>
> >> resonance with another discontinuity.  That can happen equally well
> >> at=3D3D20
> >> either end of the line.
> >>
> >> If one looks at a channel with only a TDR I might understand =3D
the=3D3D20
> >> erroneous perception that placing a discontinuity down the line =3D
is=3D3D20
> >> better than up front.  But that is an illusion.  TDR =
resolution=3D20
> falls=3D3D20
> >> with interconnect distance.  This ia a result of the inherent
loss=3D20
> of=3D3D20
> >> the interconnect that shelves bandwidth and hence resolution =3D
versus=3D3D20
> >> distance for the instrument.  This is one of the big limitations of
=3D

> a=3D3D20
> >> TDR for channel evaluation.  A through measurement with a TDT or =
=3D
VNA=3D3D20
> >> does not suffer that limitation, give true measure of S21 and so
> >> report=3D3D20
> >> the real channel performance.  Eric Bogatin spends some time on =3D
the=3D3D20
> >> issue of bandwidth versus interconnect length in his book.
> >>
> >> Regards,
> >>
> >>
> >> Steve.
> >> Stephen Zinck wrote:
> >>> Scott,
> >>> We may have some nomenclature issues here...=3D3D20
> >>>
> >>> When I say "lossy interface to the capacitor" I mean with =3D
impedance
> >>> dis=3D3D
> >> continuities. So I think we are on a similar page given your =3D
statement:
> >>>
> >>> "The only time position matters is in the face of =3D
discontinuities."
> >>>
> >>> Again, most often, my role is to simulate the customers system at
> >>> the 1=3D3D
> >> 1th hour. I don't recommend this, I just work within the customer's
> >> needs=3D3D
> >> /requirements. I make real world recommendations from simulation
> >> results =3D3D
> >> for designs where these discontinuities you mention are a fact of
> >> life. G=3D3D
> >> ranted my customers are not doing 5+ Gbit/s designs (right now ;-).
> >>>
> >>> Above these data-rates, all you mention, capacitor transition =3D
> >>> via=3D3D
> >> s, etc) are of the utmost importance. And I would absolutely agree
> >> that t=3D3D
> >> he more perfect you make these transitions, the less it matters =3D
where
> >> the=3D3D
> >> y are placed...
> >>>
> >>> So I do believe AC coupling capacitor position does matter, as you
> >>> stat=3D3D
> >> e, for the bulk of the designs occurring these days where component
> >> footp=3D3D
> >> rint and via optimization, etc. is NOT occurring...
> >>>
> >>> Steve
> >>>
> >>> Stephen P. Zinck
> >>> Interconnect Engineering Inc.
> >>> P.O. Box 577
> >>> South Berwick, ME 03908
> >>> Phone - (207) 384-8280
> >>> Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> >>> Web - www.interconnectengineering.com=3D20
> <http://www.interconnectengineering.com>
> >>>
> >>>   ----- Original Message -----=3D3D20
> >>>   From: Scott McMorrow=3D3D20
> >>>   To: Stephen Zinck=3D3D20
> >>>   Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ;
> >>> npatel@micro=3D3D
> >> n.com ; si-list@xxxxxxxxxxxxx=3D3D20
> >>>   Sent: Tuesday, September 25, 2007 11:08 AM
> >>>   Subject: Re: [SI-LIST] Re: AC Coupled Signals
> >>>
> >>>
> >>>   Steven,
> >>>
> >>>   I would not agree with your following statements.
> >>>
> >>>   "I agree in theory with all you state. Assuming a lossless
> >>> interface =3D3D
> >> to the capacitor, it shouldn't matter where you place it, given a
> >> purely =3D3D
> >> linear system. But the real world is lossy, even when one makes =3D
great
> >> 3D =3D3D
> >> solved structures. Manufacturing and other tolerances tend to take
> >> the tr=3D3D
> >> ek towards perfection to task."
> >>>
> >>>   "Would either of you agree that AC coupling capacitor location =
=3D
may
> >>> ma=3D3D
> >> tter with a lossy interface to the capacitor?"
> >>>
> >>>
> >>>   Insertion loss in a flat impedance linear lossy system will be
> >>> indepe=3D3D
> >> ndent of capacitor location.  Run the math and see.  The only time
> >> positi=3D3D
> >> on matters is in the face of discontinuities.   In fact, given a =
=3D
low
> >> loss=3D3D
> >> interconnect with discontinuities and a high loss interconnect with
> >> disc=3D3D
> >> ontinuities, the low loss system, with it's higher Q, will often =
=3D
have
> >> wor=3D3D
> >> se behavior.
> >>>
> >>>   An improperly designed 0402 capacitor transition for a 50 ohm =
=3D
line
> >>> ca=3D3D
> >> n easily exhibit a discontinuity of 35 ohms for 50 ps.  If attached
> >> to po=3D3D
> >> orly designed via transitions, the discontinuity will be even =3D
worse. =3D20
> >> Whe=3D3D
> >> n this is coupled closely to a high capacitance receiver input, a
> >> high ca=3D3D
> >> pacitance transmitter output, a low impedance via stub =3D
discontinuity,
> >> or =3D3D
> >> a low impedance connector discontinuity, it can form a 1/2 wave
> >> resonant =3D3D
> >> circuit.  This is most likely the problem you are seeing. =3D3D20
> >>>
> >>>   If the interconnect has essentially flat impedance, position =3D
does
> >>> not=3D3D
> >> matter.  If the capacitor transition is properly designed, position
> >> does=3D3D
> >> not matter.  All of the data we have on this is proprietary at this
> >> time=3D3D
> >> =3D3D2E  Our understanding of the physics has been verified by full =
=3D
wave
> >> mode=3D3D
> >> ling, simulation and measurement.
> >>>
> >>>
> >>>
> >>>   regards,
> >>>
> >>>   Scott
> >>>
> >>>
> >>>
> >>> Scott McMorrow
> >>> Teraspeed Consulting Group LLC
> >>> 121 North River Drive
> >>> Narragansett, RI 02882
> >>> (401) 284-1840 Fax
> >>>
> >>> http://www.teraspeed.com
> >>>
> >>> Teraspeed=3D3DAE is the registered service mark of
> >>> Teraspeed Consulting Group LLC
> >>>
> >>>
> >>>   Stephen Zinck wrote:=3D3D20
> >>>     Hi Scott and Steve,
> >>>
> >>>     To answer both of your questions, it is the resulting Hspice
> >>> (with =3D3D
> >> S-parameters) differential eye patterns, as viewed at the receiver
> >> die, t=3D3D
> >> hat were used to make a comparison of source versus destination AC
> >> coupli=3D3D
> >> ng capacitor locations. The system was excited with a string of =3D
ones,
> >> fol=3D3D
> >> lowed by a single zero, followed by a string of ones.=3D3D20
> >>>
> >>>     I have not specifically designed a test board that varies the
=3D
AC
> >>> co=3D3D
> >> upling capacitor location along a trace.
> >>>
> >>>     I understand the "shades of gray" here and agree that one =3D
can't
> >>> mak=3D3D
> >> e a "rule of thumb" generalization in our line of work these =3D
days.=3D3D20
> >>>
> >>>     I agree in theory with all you state. Assuming a lossless
> >>> interface=3D3D
> >> to the capacitor, it shouldn't matter where you place it, given a
> >> purely=3D3D
> >> linear system. But the real world is lossy, even when one makes =3D
great
> >> 3D=3D3D
> >> solved structures. Manufacturing and other tolerances tend to take
> >> the t=3D3D
> >> rek towards perfection to task.=3D3D20
> >>>
> >>>     Do either of you have real world measured results, that you
> >>> could s=3D3D
> >> hare, that show no marked difference in received signal
> >> characteristics w=3D3D
> >> hen the AC coupling capacitor position is varied through a 30 inch
> >> backpl=3D3D
> >> ane system (or similar)?
> >>>
> >>>     I believe my experience with capacitor location may prove true
> >>> if t=3D3D
> >> he capacitor interface is lossy (which is the case). A lot of my
> >> customer=3D3D
> >> s are just looking for quick ways to maximize performance using
> >> standard =3D3D
> >> component packages and standard layout practices (in the end, I =3D
don't
> >> lik=3D3D
> >> e to give anything away that is low lying fruit). Most of the time
=3D
I
> >> am d=3D3D
> >> oing my analysis after the board is in layout, where I have limited
> >> abili=3D3D
> >> ty to change the design (unless it is really broken). In a perfect
> >> world,=3D3D
> >> where I am involved early, the package optimization and layout
> >> structure=3D3D
> >> s can be optimized as you state, but only if the margins warrant it
> >> (syst=3D3D
> >> em performance issues are expected after initial "what-if"
> >> simulations ha=3D3D
> >> ve occurred). The right tool for the right job rules the day...
> >>>
> >>>     Would either of you agree that AC coupling capacitor location
> >>> may m=3D3D
> >> atter with a lossy interface to the capacitor?
> >>>
> >>>     All the best,
> >>>     Steve
> >>>
> >>>     Stephen P. Zinck
> >>>     Interconnect Engineering Inc.
> >>>     P.O. Box 577
> >>>     South Berwick, ME 03908
> >>>     Phone - (207) 384-8280
> >>>     Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> >>>     Web - www.interconnectengineering.com=3D20
> <http://www.interconnectengineering.com>
> >>>
> >>>       ----- Original Message -----=3D3D20
> >>>       From: Scott McMorrow=3D3D20
> >>>       To: Stephen Zinck=3D3D20
> >>>       Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ;
> >>> npatel@m=3D3D
> >> icron.com ; si-list@xxxxxxxxxxxxx=3D3D20
> >>>       Sent: Tuesday, September 25, 2007 9:44 AM
> >>>       Subject: Re: [SI-LIST] Re: AC Coupled Signals
> >>>
> >>>
> >>>       Stephen
> >>>
> >>>       Define "better" and then relate your simulations and
> >>> conclusions =3D3D
> >> to linear system theory and measurements. =3D3D20
> >>>
> >>>       I contend that the only difference an AC coupling capacitor
> >>> can p=3D3D
> >> ossibly have due to position in a linear interconnect is a result =
=3D
of
> >> impe=3D3D
> >> dance mismatch.  I contend that the capacitor will form a 1/2 wave
> >> resona=3D3D
> >> nt circuit with other interconnect discontinuities (connectors, =3D
vias
> >> stub=3D3D
> >> s, packages, Tx die, Rx die ... etc) and that this interaction is
> >> system,=3D3D
> >> chip, connector and package design dependent.  I contend that it is
> >> this=3D3D
> >> 1/2 resonance that can cause differences that can be measured, but
> >> that =3D3D
> >> there is no "rule of thumb", since the position and magnitude of
> >> disconti=3D3D
> >> nuities are different in every system.  In some systems the =3D
> >> cons=3D3D
> >> titutes a larger discontinuity than the transmitter.  In other
> >> systems th=3D3D
> >> is is reversed.  In yet other systems, connectors and vias =3D
represent
> >> larg=3D3D
> >> er discontinuites than do either the transmitters or receivers. It
> >> all "j=3D3D
> >> ust depends".  To state a specific rule is just plain incorrect.
> >>>
> >>>       I contend that once you remove the magic and myths =3D
surrounding
> >>> AC=3D3D
> >> coupling capacitors, analysis of the 3D structure shows that by
> >> reducing=3D3D
> >> the signal path discontinuity through the capacitor, you will
> >> necessaril=3D3D
> >> y improve performance.  An AC coupling capacitor, with it's
> >> associated vi=3D3D
> >> a and pad transition design, can be viewed as a black box which has
> >> inser=3D3D
> >> tion loss and return loss, and can be modeled quite well using =3D
either
> >> lum=3D3D
> >> ped element approximations or (my favorite) S-parameters.  As such
=3D
it
> >> wil=3D3D
> >> l cascade in a simulation model just like any other linear element.
=3D
=3D20
> >> If w=3D3D
> >> e start with a system with flat 50 ohm impedance from end to end, =
=3D
it
> >> can =3D3D
> >> be easily shown that no matter what the position of the capacitor
> >> along t=3D3D
> >> he interconnect is, the insertion loss of the system is identical.
=3D

> >> It is=3D3D
> >> only the return loss, as seen from each end that changes.
> >>>
> >>>       I've been designing AC coupling capacitor mounting =3D
transitions
> >>> pr=3D3D
> >> operly for quite a few years now and have some 0402 designs that =
=3D
keep
> >> S12=3D3D
> >> above -0.2 dB up to 7.5 GHz, S12 below -20 dB @ 5 GHz, and below =
=3D
-15
> >> dB =3D3D
> >> @ 10 GHz.  For all practical purposes, these designs are =3D
transparent
> >> and =3D3D
> >> may be placed anywhere in an interconnect design where there is
> >> space, si=3D3D
> >> nce there is little resonance interaction with other devices and
> >> structur=3D3D
> >> es.
> >>>
> >>>
> >>>       Scott
> >>>
> >>>
> >>> Scott McMorrow
> >>> Teraspeed Consulting Group LLC
> >>> 121 North River Drive
> >>> Narragansett, RI 02882
> >>> (401) 284-1840 Fax
> >>>
> >>> http://www.teraspeed.com
> >>>
> >>> Teraspeed=3D3DAE is the registered service mark of
> >>> Teraspeed Consulting Group LLC
> >>>    =3D3D20
> >>>
> >>>       Stephen Zinck wrote:=3D3D20
> >>>         Hi Scott,
> >>>
> >>>         My simulations show that the capacitor is best placed at =
=3D
the
> >>> re=3D3D
> >> ceiver end of the transmission-line. Do you disagree? If so, why?
> >>>
> >>>         Steve
> >>>
> >>>         Stephen P. Zinck
> >>>         Interconnect Engineering Inc.
> >>>         P.O. Box 577
> >>>         South Berwick, ME 03908
> >>>         Phone - (207) 384-8280
> >>>         Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> >>>         Web - www.interconnectengineering.com=3D20
> <http://www.interconnectengineering.com>
> >>>
> >>>           ----- Original Message -----=3D3D20
> >>>           From: Scott McMorrow=3D3D20
> >>>           To: signalintegrity@xxxxxxxxxxx=3D3D20
> >>>           Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ;
> >>> npat=3D3D
> >> el@xxxxxxxxxx ; si-list@xxxxxxxxxxxxx=3D3D20
> >>>           Sent: Tuesday, September 25, 2007 8:30 AM
> >>>           Subject: Re: [SI-LIST] Re: AC Coupled Signals
> >>>
> >>>
> >>>           Stephen,
> >>>
> >>>           I'm sorry, this is a linear system.  Except for possible
> >>> reso=3D3D
> >> nances that are created by discontinuities and modal conversion
> >> (which ha=3D3D
> >> ve absolutely zero to do with signal rise time), there is no
> >> difference i=3D3D
> >> n the attenuation of  a capacitor placed at the Tx as opposed at =
=3D
the
> >> Rx. =3D3D
> >> W.R.T. the receiver, if it is "lost in the rise-time degradation of
> >> the =3D3D
> >> system", it will be lost wherever it is placed.
> >>>
> >>>
> >>>
> >>> Scott McMorrow
> >>> Teraspeed Consulting Group LLC
> >>> 121 North River Drive
> >>> Narragansett, RI 02882
> >>> (401) 284-1840 Fax
> >>>
> >>> http://www.teraspeed.com
> >>>
> >>> Teraspeed=3D3DAE is the registered service mark of
> >>> Teraspeed Consulting Group LLC
> >>>    =3D3D20
> >>>
> >>>           Stephen Zinck wrote:=3D3D20
> >>> Hi Jory,
> >>>
> >>> I have simulated this at length and concur with your experience =
=3D
that
> >>> th=3D3D
> >> e=3D3D20
> >>> capacitor is best placed at the receiver...
> >>>
> >>> In effect, the attenuation associated with the capacitor placement
> >>> at t=3D3D
> >> he=3D3D20
> >>> of=3D3D
> >> the=3D3D20
> >>> system.
> >>> The classic "don't break it until you have to" rule is =3D
applicable...
> >>> OK=3D3D
> >> this=3D3D20
> >>> is my rule... :-)
> >>>
> >>> All the best,
> >>> Steve
> >>>
> >>> Stephen P. Zinck
> >>> Interconnect Engineering Inc.
> >>> P.O. Box 577
> >>> South Berwick, ME 03908
> >>> Phone - (207) 384-8280
> >>> Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> >>> Web - www.interconnectengineering.com=3D20
> <http://www.interconnectengineering.com>
> >>>
> >>> ----- Original Message -----=3D3D20
> >>> From: "Jory McKinley" <jory_mckinley@xxxxxxxxx>
> >>> To: <leeritchey@xxxxxxxxxxxxx>; <npatel@xxxxxxxxxx>;
> >>> <si-list@freelists=3D3D
> >> =3D3D2Eorg>
> >>> Sent: Monday, September 24, 2007 5:31 PM
> >>> Subject: [SI-LIST] Re: AC Coupled Signals
> >>>
> >>>
> >>>   I will elaborate a bit on what I have seen. I have measured =3D
(time
> >>> dom=3D3D
> >> ain)=3D3D20
> >>> in the lab some effects that appears to be location specific in =
=3D
the=3D3D20
> >>> placement of the AC coupling caps at the rcvr.  Now this may be =
=3D
due
> >>> in =3D3D
> >> part=3D3D20
> >>> to the fact that I am using 50-ohm resistor termination in each =
=3D
> >>> as=3D3D
> >> =3D3D20
> >>> well and the combination (cap plus rcvr reflection) is giving =3D
some=3D3D20
> >>> imbalance depending on distance.  The best rcvr eye that I am =3D
seeing
> >>> is=3D3D
> >> =3D3D20
> >>> when I can move the AC/term as close to the rcvr as I can.  By the
> >>> way =3D3D
> >>
> >>> these are 5Gb/s signals.
> >>> If I have time I will try and isolate what I am seeing and even
> >>> simulat=3D3D
> >> e=3D3D20
> >>> it, has anyone else seen or simulated this?
> >>> -Jory
> >>>
> >>> ----- Original Message ----
> >>> From: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
> >>> To: "npatel@xxxxxxxxxx" <npatel@xxxxxxxxxx>; si-list@xxxxxxxxxxxxx
> >>> Sent: Monday, September 24, 2007 1:06:06 PM
> >>> Subject: [SI-LIST] Re: AC Coupled Signals
> >>>
> >>> Nikil,
> >>>
> >>> I have made measurements on test PCBs and the location is not all
=3D
that
> >>> important.  In identical pairs, one with AC coupling capacitors =
=3D
and
> >>> the=3D3D
> >>
> >>> other without, the loss vs. frequency is virtually identical at =
=3D
leas
> >>> ou=3D3D
> >> t=3D3D20
> >>> to
> >>> 6 GHz.  That would be 12 Mb/S.
> >>>
> >>> Lee Ritchey
> >>>
> >>>
> >>>     [Original Message]
> >>> From: <npatel@xxxxxxxxxx>
> >>> To: <si-list@xxxxxxxxxxxxx>
> >>> Date: 9/24/2007 10:21:37 AM
> >>> Subject: [SI-LIST] AC Coupled Signals
> >>>
> >>> Hi all,
> >>> In case of AC coupled signals does anyone know of an optimum =3D
placement
> >>> for the caps? I mean should they be placed near the source, =3D
> >>> middle of  the transmission line?
> >>> How much difference does it make in the opening of the eye?
> >>> The signals are differential CML running at 3.0Gbps
> >>>
> >>> Thanks,
> >>> Nikhil
> >>>
> >>>

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