[SI-LIST] Re: AC Coupled Signals
- From: "Stephen Zinck" <signalintegrity@xxxxxxxxxxx>
- To: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Tue, 25 Sep 2007 11:38:37 -0400
Scott,
We may have some nomenclature issues here...
When I say "lossy interface to the capacitor" I mean with impedance
discontinuities. So I think we are on a similar page given your statement:
"The only time position matters is in the face of discontinuities."
Again, most often, my role is to simulate the customers system at the 11th
hour. I don't recommend this, I just work within the customer's
needs/requirements. I make real world recommendations from simulation results
for designs where these discontinuities you mention are a fact of life. Granted
my customers are not doing 5+ Gbit/s designs (right now ;-).
Above these data-rates, all you mention, capacitor transition (pad, vias, etc)
are of the utmost importance. And I would absolutely agree that the more
perfect you make these transitions, the less it matters where they are placed...
So I do believe AC coupling capacitor position does matter, as you state, for
the bulk of the designs occurring these days where component footprint and via
optimization, etc. is NOT occurring...
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----
From: Scott McMorrow
To: Stephen Zinck
Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ; npatel@xxxxxxxxxx ;
si-list@xxxxxxxxxxxxx
Sent: Tuesday, September 25, 2007 11:08 AM
Subject: Re: [SI-LIST] Re: AC Coupled Signals
Steven,
I would not agree with your following statements.
"I agree in theory with all you state. Assuming a lossless interface to the
capacitor, it shouldn't matter where you place it, given a purely linear
system. But the real world is lossy, even when one makes great 3D solved
structures. Manufacturing and other tolerances tend to take the trek towards
perfection to task."
"Would either of you agree that AC coupling capacitor location may matter
with a lossy interface to the capacitor?"
Insertion loss in a flat impedance linear lossy system will be independent of
capacitor location. Run the math and see. The only time position matters is
in the face of discontinuities. In fact, given a low loss interconnect with
discontinuities and a high loss interconnect with discontinuities, the low loss
system, with it's higher Q, will often have worse behavior.
An improperly designed 0402 capacitor transition for a 50 ohm line can easily
exhibit a discontinuity of 35 ohms for 50 ps. If attached to poorly designed
via transitions, the discontinuity will be even worse. When this is coupled
closely to a high capacitance receiver input, a high capacitance transmitter
output, a low impedance via stub discontinuity, or a low impedance connector
discontinuity, it can form a 1/2 wave resonant circuit. This is most likely
the problem you are seeing.
If the interconnect has essentially flat impedance, position does not matter.
If the capacitor transition is properly designed, position does not matter.
All of the data we have on this is proprietary at this time. Our understanding
of the physics has been verified by full wave modeling, simulation and
measurement.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Stephen Zinck wrote:
Hi Scott and Steve,
To answer both of your questions, it is the resulting Hspice (with
S-parameters) differential eye patterns, as viewed at the receiver die, that
were used to make a comparison of source versus destination AC coupling
capacitor locations. The system was excited with a string of ones, followed by
a single zero, followed by a string of ones.
I have not specifically designed a test board that varies the AC coupling
capacitor location along a trace.
I understand the "shades of gray" here and agree that one can't make a
"rule of thumb" generalization in our line of work these days.
I agree in theory with all you state. Assuming a lossless interface to the
capacitor, it shouldn't matter where you place it, given a purely linear
system. But the real world is lossy, even when one makes great 3D solved
structures. Manufacturing and other tolerances tend to take the trek towards
perfection to task.
Do either of you have real world measured results, that you could share,
that show no marked difference in received signal characteristics when the AC
coupling capacitor position is varied through a 30 inch backplane system (or
similar)?
I believe my experience with capacitor location may prove true if the
capacitor interface is lossy (which is the case). A lot of my customers are
just looking for quick ways to maximize performance using standard component
packages and standard layout practices (in the end, I don't like to give
anything away that is low lying fruit). Most of the time I am doing my analysis
after the board is in layout, where I have limited ability to change the design
(unless it is really broken). In a perfect world, where I am involved early,
the package optimization and layout structures can be optimized as you state,
but only if the margins warrant it (system performance issues are expected
after initial "what-if" simulations have occurred). The right tool for the
right job rules the day...
Would either of you agree that AC coupling capacitor location may matter
with a lossy interface to the capacitor?
All the best,
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----
From: Scott McMorrow
To: Stephen Zinck
Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ;
npatel@xxxxxxxxxx ; si-list@xxxxxxxxxxxxx
Sent: Tuesday, September 25, 2007 9:44 AM
Subject: Re: [SI-LIST] Re: AC Coupled Signals
Stephen
Define "better" and then relate your simulations and conclusions to
linear system theory and measurements.
I contend that the only difference an AC coupling capacitor can possibly
have due to position in a linear interconnect is a result of impedance
mismatch. I contend that the capacitor will form a 1/2 wave resonant circuit
with other interconnect discontinuities (connectors, vias stubs, packages, Tx
die, Rx die ... etc) and that this interaction is system, chip, connector and
package design dependent. I contend that it is this 1/2 resonance that can
cause differences that can be measured, but that there is no "rule of thumb",
since the position and magnitude of discontinuities are different in every
system. In some systems the receiver constitutes a larger discontinuity than
the transmitter. In other systems this is reversed. In yet other systems,
connectors and vias represent larger discontinuites than do either the
transmitters or receivers. It all "just depends". To state a specific rule is
just plain incorrect.
I contend that once you remove the magic and myths surrounding AC
coupling capacitors, analysis of the 3D structure shows that by reducing the
signal path discontinuity through the capacitor, you will necessarily improve
performance. An AC coupling capacitor, with it's associated via and pad
transition design, can be viewed as a black box which has insertion loss and
return loss, and can be modeled quite well using either lumped element
approximations or (my favorite) S-parameters. As such it will cascade in a
simulation model just like any other linear element. If we start with a system
with flat 50 ohm impedance from end to end, it can be easily shown that no
matter what the position of the capacitor along the interconnect is, the
insertion loss of the system is identical. It is only the return loss, as seen
from each end that changes.
I've been designing AC coupling capacitor mounting transitions properly
for quite a few years now and have some 0402 designs that keep S12 above -0.2
dB up to 7.5 GHz, S12 below -20 dB @ 5 GHz, and below -15 dB @ 10 GHz. For all
practical purposes, these designs are transparent and may be placed anywhere in
an interconnect design where there is space, since there is little resonance
interaction with other devices and structures.
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Stephen Zinck wrote:
Hi Scott,
My simulations show that the capacitor is best placed at the receiver
end of the transmission-line. Do you disagree? If so, why?
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----
From: Scott McMorrow
To: signalintegrity@xxxxxxxxxxx
Cc: jory_mckinley@xxxxxxxxx ; leeritchey@xxxxxxxxxxxxx ;
npatel@xxxxxxxxxx ; si-list@xxxxxxxxxxxxx
Sent: Tuesday, September 25, 2007 8:30 AM
Subject: Re: [SI-LIST] Re: AC Coupled Signals
Stephen,
I'm sorry, this is a linear system. Except for possible resonances
that are created by discontinuities and modal conversion (which have absolutely
zero to do with signal rise time), there is no difference in the attenuation of
a capacitor placed at the Tx as opposed at the Rx. W.R.T. the receiver, if it
is "lost in the rise-time degradation of the system", it will be lost wherever
it is placed.
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Stephen Zinck wrote:
Hi Jory,
I have simulated this at length and concur with your experience that the
capacitor is best placed at the receiver...
In effect, the attenuation associated with the capacitor placement at the
receiver (parasitics/pads/vias) is lost in the rise-time degradation of the
system.
The classic "don't break it until you have to" rule is applicable... OK this
is my rule... :-)
All the best,
Steve
Stephen P. Zinck
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
----- Original Message -----
From: "Jory McKinley" <jory_mckinley@xxxxxxxxx>
To: <leeritchey@xxxxxxxxxxxxx>; <npatel@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Monday, September 24, 2007 5:31 PM
Subject: [SI-LIST] Re: AC Coupled Signals
I will elaborate a bit on what I have seen. I have measured (time domain)
in the lab some effects that appears to be location specific in the
placement of the AC coupling caps at the rcvr. Now this may be due in part
to the fact that I am using 50-ohm resistor termination in each lead as
well and the combination (cap plus rcvr reflection) is giving some
imbalance depending on distance. The best rcvr eye that I am seeing is
when I can move the AC/term as close to the rcvr as I can. By the way
these are 5Gb/s signals.
If I have time I will try and isolate what I am seeing and even simulate
it, has anyone else seen or simulated this?
-Jory
----- Original Message ----
From: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
To: "npatel@xxxxxxxxxx" <npatel@xxxxxxxxxx>; si-list@xxxxxxxxxxxxx
Sent: Monday, September 24, 2007 1:06:06 PM
Subject: [SI-LIST] Re: AC Coupled Signals
Nikil,
I have made measurements on test PCBs and the location is not all that
important. In identical pairs, one with AC coupling capacitors and the
other without, the loss vs. frequency is virtually identical at leas out
to
6 GHz. That would be 12 Mb/S.
Lee Ritchey
[Original Message]
From: <npatel@xxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Date: 9/24/2007 10:21:37 AM
Subject: [SI-LIST] AC Coupled Signals
Hi all,
In case of AC coupled signals does anyone know of an optimum placement
for the caps? I mean should they be placed near the source, receiver,
middle of the transmission line?
How much difference does it make in the opening of the eye?
The signals are differential CML running at 3.0Gbps
Thanks,
Nikhil
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