[PCB_FORUM] Re: electrical constraint manager, timing

From: <sjcharles@xxxxxxx>
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Date: Wed, 6 Jul 2005 13:13:12 -0400
Austin, thanks for you time again.We set up the pin-pair, from bga to connector 
on right side of pdf file which i attached and hopefully will get through. The 
lower trace is the clk line and the upper trace is the data line. We are using 
daisy chain topology, with clock line lenght set to 2500 mils.> then i set up 
the match set with the clk set as target. clk line starts from bga to tqfp, 
surface mount test connector and ends at the samtec connector on right side. I 
think i'm going to get rid of the match set and set all the data line to be 200 
mils longer than the clk line. 
sam
From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> Date: 2005/07/05 Tue PM 08:19:25 EDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> 
> Hi Sam,
> 
> I assumed these nets were just two nodes...probably a bad assumption.  What,
> exactly, is the topology?  What is the interface being used for?
> 
> Regards,
> 
> Austin
> 
> > I think i may be a little slow, I guess i could make trace length
> > of clk line 2300 to 2500 and make the data lines 2500 to 2700.
> > I'll try tomorrow.
> > >
> > > From: "Ken Kiplinger" <kkiplinger@xxxxxxxxxxxxxxxxxxx>
> > > Date: 2005/07/05 Tue PM 04:41:03 EDT
> > > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > >
> > >
> > >     It depends on the structure of the nets. If they are all 2
> > pins, then it doesn't matter. IF you have the voltage nets all
> > assigned, then it will ignore stubs to res, etc. If you set the
> > delay for a pin pair, then the whole net may be longer if there
> > is more than just 2 pins in the net. Does that make sense? The
> > delta specified is to make the net shorter (with a positive delta
> > entered). Either way, the differences that you are showing in you
> > net lengths don't add up unless there is extra length to a stub
> > or T. The best way, if they aren't 2 pin nets, is to specify the
> > pin pairs in the spreadsheet, and copy the values for each pin pair.
> > >     If you are assigning the lengths, and there are mixed net
> > topographies, then assigning the pin pairs is a must.
> > >  Ken Kiplinger
> > >
> > > -----Original Message-----
> > > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> > > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
> > > sjcharles@xxxxxxx
> > > Sent: Tuesday, July 05, 2005 12:57 PM
> > > To: icu-pcb-forum@xxxxxxxxxxxxx
> > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > >
> > >
> > > Sorry with all the questions but which setting works well for
> > pin pairs? I'm using longest Pin Pair.
> > > >
> > > > From: "Ken Kiplinger" <kkiplinger@xxxxxxxxxxxxxxxxxxx>
> > > > Date: 2005/07/05 Tue PM 03:05:50 EDT
> > > > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > > >
> > > > 0 delta would be the target. Just skip it, and only assign
> > the tolerance.
> > > >   Ken Kiplinger
> > > >   Design Solutions, Inc.
> > > >
> > > > -----Original Message-----
> > > > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> > > > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
> > > > sjcharles@xxxxxxx
> > > > Sent: Tuesday, July 05, 2005 11:52 AM
> > > > To: icu-pcb-forum@xxxxxxxxxxxxx
> > > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > > >
> > > >
> > > > we must have different software because i can't get 0 delta
> > and 200 tolerance the program gives me a "invalid" error message.
> > > > Sam
> > > > >
> > > > > From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> > > > > Date: 2005/07/05 Tue PM 02:36:13 EDT
> > > > > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > > > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > > > >
> > > > > Hi Sam,
> > > > >
> > > > > I can't help you with the autorouter...just the Constraint
> > Manager and the
> > > > > interactive router...  I think you have it set-up almost
> > right.  Set PCLK in
> > > > > Total Etch Length to 2500 min and 2700 max (that is your
> > 2.5" =/- .2"...did
> > > > > you mean =/- or +/-?), and then set-up a match group in
> > relative propagation
> > > > > delay with PCLK as your target.  But, I would set your
> > group match length to
> > > > > 0:200 (delta of 0, tolerance of 200), and that should give
> > you the length
> > > > > match to +-200 to the target.
> > > > >
> > > > > When you specify the tolerance in relative prop delay, you
> > can set it in the
> > > > > column for the group heading, and that applies it to the
> > entire group...then
> > > > > make sure PCLK is set to be the target.
> > > > >
> > > > > Regards,
> > > > >
> > > > > Austin
> > > > >
> > > > > > Thanks Austin, I need the pclk to arrive to its destination a
> > > > > > little before the data lines, i'm told the CLK line can be about
> > > > > > 2.5 inches long =/- .200 inches. With those contraints i went to
> > > > > > the NET folder under Total Etch Length i put min 2500 and max
> > > > > > 2600 for pclk just to see how the router would do. Then i set up
> > > > > > the relative prop delays with the data lines.
> > > > > > I think i set those up correctly.
> > > > > > I made the PCLK (2.5 in) the target and the data lines 200 mil:10
> > > > > > mil. Which i'm told represents 200 mil longer or shorter than the
> > > > > > 2.5 in PCLK.
> > > > > > I did the pin pair and match group and i think everything is set
> > > > > > up right, but when i push the autoroute button my total etch
> > > > > > length are about 1000 mil over.
> > > > > > thanks again for your time.
> > > > > > Sam
> > > > > > >
> > > > > > > From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> > > > > > > Date: 2005/07/04 Mon PM 09:17:56 EDT
> > > > > > > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > > > > > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > > > > > >
> > > > > > > Hi Sam,
> > > > > > >
> > > > > > > > I set the clock up in in ecset in NETS folder.PCLK is
> > set up to
> > > > > > > > be 2300-2500 mils in length. The delta tolerance for
> > the rest of
> > > > > > > > the match group is 200mils =/- 10 mils. Yet when i
> > auto route my
> > > > > > > > clk is about 3000 mils and the rest fo the match
> > group are about
> > > > > > > > 4500 mils. Where do i set up the prop delay of the PCLK?
> > > > > > >
> > > > > > > I'm not clear on exactly what you are doing here, and perhaps
> > > > > > on what you
> > > > > > > are trying to do.  Do you want a relative delay group (all the
> > > > > > signals are
> > > > > > > simply relative to each other or to one signal...the target),
> > > > > > or do you want
> > > > > > > them to all be fixed lengths (between a min and a max
> > absolute length)?
> > > > > > >
> > > > > > > It sounds to me (which is contrary to what I thought you
> > > > > > wanted), that you
> > > > > > > need specific lengths.  If you do, then you don't use relative
> > > > > > prop delay,
> > > > > > > but total etch length.  Let me know what you are trying
> > to do, and I can
> > > > > > > tell you how to do it.  I believe you only need to use
> > one, total etch
> > > > > > > length or relative prop delay.
> > > > > > >
> > > > > > > Regards,
> > > > > > >
> > > > > > > Austin
> > > > > > >
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[PCB_FORUM] Re: electrical constraint manager, timing

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