[PCB_FORUM] Re: electrical constraint manager, timing

  • From: sjchar3@xxxxxxxxxxxx
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Tue, 14 Feb 2006 11:20:41 -0500

http://www.us.design-reuse.com/news/news12571.html 
 
i guess this is officially release.
 

-----Original Message-----
From: Austin Franklin <austin@xxxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
Sent: Thu, 30 Jun 2005 11:28:44 -0400
Subject: [PCB_FORUM] Re: electrical constraint manager, timing


Under net/routing/relative prop delay, set up a group that contains your
clock and other signals you want related to this clock.  Set the group match
length value in the group name heading under "delta:tolerance", such as
"0:-300" (note the "=", typically 300 will mean +- 300), and it will then be
assigned to all the signals in that group.  Then, select the clock and set
it as "target".

Regards,

Austin

> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
> sjcharles@xxxxxxx
> Sent: Thursday, June 30, 2005 11:12 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] electrical constraint manager, timing
>
>
> Group: how do i set up a constraint for my clock signal to arrive
> at it destination where it is equal to or less the arrival of the
> data signals.
> I'm using pcb si 610. any suggestions would be appreciated.
> Thanks, Sam

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