[PCB_FORUM] Re: electrical constraint manager, timing

From: <sjcharles@xxxxxxx>
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Date: Tue, 5 Jul 2005 16:15:23 -0400
Group:
Here are two nets. It seems the pclk is following the rules but the data lines 
are way off. I set the delta to 0 and the tolerance to 200. Pipe_clk is the 
target. BTW i don't get DRC errors. I'm going to try and re-enter the match 
group info. 
Thanks again, Sam. 
 Net Name:       PIPE_0_PCLK

  Via Count:              4
  Total Etch Length:      2699.142 MIL
  Total Manhattan Length: 2576.304 MIL
  Percent Manhattan:      104.77%

Net Name:       PIPE_0_RXDK1

  Via Count:              6
  Total Etch Length:      3812.34 MIL
  Total Manhattan Length: 3638.598 MIL
  Percent Manhattan:      104.77%

> 
> From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> Date: 2005/07/05 Tue PM 02:36:13 EDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> 
> Hi Sam,
> 
> I can't help you with the autorouter...just the Constraint Manager and the
> interactive router...  I think you have it set-up almost right.  Set PCLK in
> Total Etch Length to 2500 min and 2700 max (that is your 2.5" =/- .2"...did
> you mean =/- or +/-?), and then set-up a match group in relative propagation
> delay with PCLK as your target.  But, I would set your group match length to
> 0:200 (delta of 0, tolerance of 200), and that should give you the length
> match to +-200 to the target.
> 
> When you specify the tolerance in relative prop delay, you can set it in the
> column for the group heading, and that applies it to the entire group...then
> make sure PCLK is set to be the target.
> 
> Regards,
> 
> Austin
> 
> > Thanks Austin, I need the pclk to arrive to its destination a
> > little before the data lines, i'm told the CLK line can be about
> > 2.5 inches long =/- .200 inches. With those contraints i went to
> > the NET folder under Total Etch Length i put min 2500 and max
> > 2600 for pclk just to see how the router would do. Then i set up
> > the relative prop delays with the data lines.
> > I think i set those up correctly.
> > I made the PCLK (2.5 in) the target and the data lines 200 mil:10
> > mil. Which i'm told represents 200 mil longer or shorter than the
> > 2.5 in PCLK.
> > I did the pin pair and match group and i think everything is set
> > up right, but when i push the autoroute button my total etch
> > length are about 1000 mil over.
> > thanks again for your time.
> > Sam
> > >
> > > From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> > > Date: 2005/07/04 Mon PM 09:17:56 EDT
> > > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > > Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> > >
> > > Hi Sam,
> > >
> > > > I set the clock up in in ecset in NETS folder.PCLK is set up to
> > > > be 2300-2500 mils in length. The delta tolerance for the rest of
> > > > the match group is 200mils =/- 10 mils. Yet when i auto route my
> > > > clk is about 3000 mils and the rest fo the match group are about
> > > > 4500 mils. Where do i set up the prop delay of the PCLK?
> > >
> > > I'm not clear on exactly what you are doing here, and perhaps
> > on what you
> > > are trying to do.  Do you want a relative delay group (all the
> > signals are
> > > simply relative to each other or to one signal...the target),
> > or do you want
> > > them to all be fixed lengths (between a min and a max absolute length)?
> > >
> > > It sounds to me (which is contrary to what I thought you
> > wanted), that you
> > > need specific lengths.  If you do, then you don't use relative
> > prop delay,
> > > but total etch length.  Let me know what you are trying to do, and I can
> > > tell you how to do it.  I believe you only need to use one, total etch
> > > length or relative prop delay.
> > >
> > > Regards,
> > >
> > > Austin
> > >
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[PCB_FORUM] Re: electrical constraint manager, timing

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