[PCB_FORUM] Re: electrical constraint manager, timing

From: "Ken Kiplinger" <kkiplinger@xxxxxxxxxxxxxxxxxxx>
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Date: Tue, 5 Jul 2005 11:12:49 -0700
Sam,
   Do you have length DRC's after the autoroute? Maybe the router can't find a 
way to match your traces. If there are no DRC's then you have a problem, but if 
the DRC's exist, then you could have put the constraints in correctly. 
 Ken Kiplinger
 Design Solutions, Inc.

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of
sjcharles@xxxxxxx
Sent: Tuesday, July 05, 2005 10:58 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: electrical constraint manager, timing


Thanks Austin, I need the pclk to arrive to its destination a little before the 
data lines, i'm told the CLK line can be about 2.5 inches long =/- .200 inches. 
With those contraints i went to the NET folder under Total Etch Length i put 
min 2500 and max 2600 for pclk just to see how the router would do. Then i set 
up the relative prop delays with the data lines. 
I think i set those up correctly. 
I made the PCLK (2.5 in) the target and the data lines 200 mil:10 mil. Which 
i'm told represents 200 mil longer or shorter than the 2.5 in PCLK. 
I did the pin pair and match group and i think everything is set up right, but 
when i push the autoroute button my total etch length are about 1000 mil over.
thanks again for your time.
Sam
> 
> From: "Austin Franklin" <austin@xxxxxxxxxxxx>
> Date: 2005/07/04 Mon PM 09:17:56 EDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: electrical constraint manager, timing
> 
> Hi Sam,
> 
> > I set the clock up in in ecset in NETS folder.PCLK is set up to
> > be 2300-2500 mils in length. The delta tolerance for the rest of
> > the match group is 200mils =/- 10 mils. Yet when i auto route my
> > clk is about 3000 mils and the rest fo the match group are about
> > 4500 mils. Where do i set up the prop delay of the PCLK?
> 
> I'm not clear on exactly what you are doing here, and perhaps on what you
> are trying to do.  Do you want a relative delay group (all the signals are
> simply relative to each other or to one signal...the target), or do you want
> them to all be fixed lengths (between a min and a max absolute length)?
> 
> It sounds to me (which is contrary to what I thought you wanted), that you
> need specific lengths.  If you do, then you don't use relative prop delay,
> but total etch length.  Let me know what you are trying to do, and I can
> tell you how to do it.  I believe you only need to use one, total etch
> length or relative prop delay.
> 
> Regards,
> 
> Austin
> 
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[PCB_FORUM] Re: electrical constraint manager, timing

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